• Asian Pacific Journal of Cancer Prevention
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• v.13 no.8
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• pp.3637-3643
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• 2012

Objective: Non-homologous end joining (NHEJ) is a pathway for repairing DNA double-strand breaks. Recent publications indicated that XRCC5, XRCC6 and XRCC7 genes may participate in the pathogenesis of breast cancer. The aim of this Human Genome Epidemiology (HuGE) review and meta-analysis was to investigate associations between XRCC5, XRCC6 and XRCC7 genetic polymorphisms in the NHEJ pathway and breast cancer risk. Methods: Studies focusing on the relationship between genetic polymorphisms in XRCC5, XRCC6 and XRCC7 genes and susceptibility to breast cancer were selected from the Pubmed, Cochrane library, Embase, Web of Science, Springerlink, CNKI and CBM databases. Data were extracted by two independent reviewers. The meta-analysis was performed with Review Manager Version 5.1.6 and STATA Version 12.0 software. The odds ratio (OR) with 95% confidence interval (95%CI) was calculated based on the extracted data. Results: According to the inclusion criteria, we final included seven studies with a total of 2,864 breast cancer cases and 3,060 healthy controls. Meta-analysis results showed that rs3835 (G>A) and rs828907 (G>T) in XRCC5 gene, and rs132793 (G>A) in XRCC6 gene might increase the risk of breast cancer, while rs132788 G>T and rs6002421 (A>G) might be protective factors. However, there was no relationship between XRCC7 genetic polymorphisms and the risk of breast cancer. Conclusion: This meta-analysis suggests that the rs3835 G>A and rs828907 G>T in XRCC5 gene, rs6002421 (A>G), rs132788 (G>T) and rs132793 (G>A) in XRCC6 gene might be risk factors for breast cancer, while the rs132788 (G>T) and rs6002421 (A>G) in XRCC6 gene might be protective.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.29-38
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• 2009

In this paper, a high performance pipelined computing design of parallel multiplier-temporal buffer-parallel accumulator is present for the convolution-based non-cascaded architecture aiming at the real time Discrete Wavelet Transform(DWT) processing. The convolved multiplication of DWT would be reduced upto 1/4 by utilizing the filter coefficients symmetry and the up/down sampling; and it could be dealt with 3-5 times faster computation by LUT-based DA multiplication of multiple filter coefficients parallelized for product terms with an image data. Further, the reutilization of computed product terms could be achieved by storing in the temporal buffer, which yields the saving of computation as well as dynamic power by 50%. The convolved product terms of image data and filter coefficients are realigned and stored in the temporal buffer for the accumulated addition. Then, the buffer management of parallel aligned storage is carried out for the high speed sequential retrieval of parallel accumulations. The convolved computation is pipelined with parallel multiplier-temporal buffer-parallel accumulation in which the parallelization of temporal buffer and accumulator is optimize, with respect to the performance of parallel DA multiplier, to improve the pipelining performance. The proposed architecture is back-end designed with 0.18um library, which verifies the 30fps throughput of SVGA(800$\times$600) images at 90MHz.

• Journal of Korean Clinical Health Science
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• v.2 no.1
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• pp.35-45
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• 2014

Purpose: This study analyzes occupational therapy interventions to improve activities of daily living (ADL) in dementia patients and the instruments used to verify their effects through a systematic review and attempts to use the results as preliminary data in selecting further interventions and instruments. Method: The databases searched included NDSL, DBpia, RISS, KISS and National Assembly Library with search words including 'Alzheimer's disease', 'Alzheimer', 'daily living' and 'ADL.' The subjects of analysis were a total of 7 studies, and a frequency analysis was used for the usage count of the interventions used in each study. In order to provide evidence, PICO Method was used for sorting. Result: As a result of this study, there were 7 occupational therapy interventions applied to improve ADL in dementia patients, which were used 7 times total. As for the instruments used to validate the effects of the interventions for the ADL, it turned out that '3 studies used AMPS (42.9%),' which was the most, followed by 'Allen Cognitive Level Screen' (ACLS) and Functional Independence Measure' (FIM), respectively used in 2 studies (28.6%); and 'Modified Barthel Index' (MBI) and 'Philadelphia Geriatric Center IADL' (PGC IADL), respectively used in 1 study. Regarding the qualitative level of evidence, it turned out that 4 studies were Level III (57.1%), followed by 2 studies at Level IV (28.6%) and 1 study at Level I (14.3%). Conclusion: This study suggested the kinds and frequencies of usage of the interventions and instruments of occupational therapy for the improvement of ADL in dementia patients, and the studies of evidence were presented by the PICO Method. It is judged that the results of this study can be used as preliminary data in selecting interventions and instruments to improve the ADL in dementia patients. In the future, studies should be carried out on the ADL in other areas related to dementia.

• Journal of Broadcast Engineering
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• v.18 no.2
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• pp.204-214
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• 2013

Recently various research have been conducted relating to the implementation of signal processing or communication system by software using the massively parallel processing capability of the GPU. In this work, we focus on reducing software simulation time of 2K/8K FFT in DVB-T by using GPU. we estimate the processing time of the DVB-T system, which is one of the standards for DTV transmission, by CPU. Then we implement the FFT processing by the software using the NVIDIA's massively parallel GPU processor. In this paper we apply stream process method to reduce the overhead for data transfer between CPU and GPU, coalescing method to reduce the global memory access time and data structure design method to maximize the shared memory usage. The results show that our proposed method is approximately 20~30 times as fast as the CPU based FFT processor, and approximately 1.8 times as fast as the CUFFT library (version 2.1) which is provided by the NVIDIA when applied to the DVB-T 2K/8K mode FFT.

• Journal of Practical Engineering Education
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• v.12 no.1
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• pp.213-230
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• 2020

Until now, various educational budgets, facilities, and programs have been put into school education, but the results have not been clearly evaluated. This study presents a model to analyze the effectiveness of educational support for students in high schools across the country. In this model, we first use EM cluster analysis to make clusters with similar inputs for school operation, and then calculate the relative efficiency in each cluster by using Network DEA analysis. The Network DEA analysis has a two-stage structure where the first stage uses six inputs in terms of school infrastructure to generate outputs such as the number of academic persistence. In the Network DEA analysis, the second stage uses 10 inputs in terms of school programs to generate outputs such as the number of enrollees to higher learning and the number of employees and per capita usage of library as the connection variable. Based on the efficiency analysis results, Tier analysis is performed by applying the Euclidean distance to select targets for benchmarking. In this study, we applied the model to analyze the efficiency of educational support by collecting data regarding student education support in general and vocational high school nationwide. The stepwise benchmarking method proposed that the target be selected for efficiency improvement step by step, taking into account inefficient school elements to complement the problem of the choice of benchmarking targets. Based on this study, it is expected that schools with low efficiency of educational support for students will be used as basic data for stepwise benchmarking for efficient operation of educational support for students.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.557-565
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• 2005

This paper presents the development and implementation of a zero-copy file transfer mechanism that improves the efficiency of file transfers for PC cluster systems using hardware-based VIA(Virtual Interface Architecture) network adapters. VIA is one of the representative user-level communication interfaces, but because there is no library for file transfer, one copy occurs between kernel buffer and user boilers. Our mechanism presents a file transfer primitive that does not require the file system to be modified and allows the NIC to transfer data from the kernel buffer to the remote node directly without copying. To do this, we have developed a hardware-based VIA network adapter, which supports the PCI 64bit/66MHz bus and Gigabit Ethernet, as a NIC, and implemented a zero-copy file transfer mechanism. The experimental results show that the overhead of data coy and context switching in the sender is greatly reduced and the CPU utilization of the sender is reduced to $30\%\~40\%$ of the VIA send/receive mechanism. We demonstrate the performance of the zero-copy file transfer mechanism experimentally. and compare the results with those from existing file transfer mechanisms.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11C
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• pp.1077-1087
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• 2003

In this paper, we proposed an architecture of a cryptosystem with various operating modes for the network security and implemented in hardware using the ASIC library. For configuring a cryptosystem, the standard block ciphers such as AES, SEED and 3DES were included. And the implemented cryptosystem can encrypt and decrypt the data in real time through the wired/wireless network with the minimum latency time (minimum 64 clocks, maximum 256 clocks). It can support CTR mode which is widely used recently as well as the conventional block cipher modes such as ECB, CBC and OFB, and operates in the multi-bit mode (64, 128, 192, and 256 bits). The implemented hardware has the expansion possibility for the other algorithms according to the network security protocol such as IPsec and the included ciphering blocks can be operated simultaneously. The self-ciphering mode and various ciphering mode can be supported by the hardware sharing and the programmable data-path. The global operation is programmed by the serial communication port and the operation is decided by the control signals decoded from the instruction by the host. The designed hardware using VHDL was synthesized with Hynix 0.25$\mu\textrm{m}$ CMOS technology and it used the about 100,000 gates. Also we could assure the stable operation in the timing simulation over 100㎒ using NC-verilog.

• Journal of Acupuncture Research
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• v.35 no.4
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• pp.158-168
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• 2018

The purpose of this study was to review clinical studies of lumbar herniated intervertebral disc (LHIVD) treatment using acupuncture. Online database (PubMed, COCHRANE Library, EMBASE, CNKI, KISS, NDSL, KoreaMed, KMbase, OASIS, and KISTI) searches were conducted in May 2018. Studies that used acupuncture, electroacupuncture or warm needle acupuncture were included, along with participants who had lower back pain and radiating pain of their lower limbs consistent with radiological findings. Animal studies and nonclinical data were excluded. Data on treatment methods, site, time, frequency, period, and scales used were analyzed. There were 69 studies including 38 randomized controlled trials, 14 retrospective observational studies, and 17 clinical case studies. There were 51 acupoints selected for acupuncture treatment of LHIVD. The most frequently treated acupoints were BL23, BL25, BL24, and BL40. The mean treatment time, frequency, and duration were $26.06{\pm}6.70$ mins, $6.29{\pm}1.70$ times/week, and $20.57{\pm}11.04$ days, respectively, in randomized controlled trials (RCT), and $18.62{\pm}4.60$ mins, $11.58{\pm}3.99$ times/week, and $34.43{\pm}17.62$ days, respectively, in case/retrospective studies ($mean{\pm}SD$). This review collates information about acupuncture treatment methods for LHIVD.

• The Journal of Korean Academy of Sensory Integration
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• v.12 no.2
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• pp.25-36
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• 2014

Objective : The purpose of this study is learning the characteristics of literature applying single subject researches in the field of sensory integration therapy of Korean occupational therapy and evaluating the quality level of them. Methods : Analyzed the characteristics of 17 single subject research papers (independent variable, study design, study subject, total number of session, study period, intervention time, intervention place, dependent variable, measuring tool and result) published between 2002 and 2013 using the document delivery service of Korean Society of Occupational Therapy, National Discovery for Science Leaders (NDSL), Nuri Media (DBpia), Research Information Sharing Service (RISS), Korean Studies Information Service System (KISS) and National Assembly Library and evaluated the literatures using quality evaluation scale. Results : According to the analysis result on the literature characteristics, reversal design was the most used study method. Total number of session was 10 sessions to 34 sessions. Study period was 4 weeks to 16 weeks. Intervention time was 8 minutes to 70 minutes and most interventions were done in occupational therapy room or sensory integration therapy room. According to the result of quality level evaluation, 4 papers out of 17 papers were on high level and remaining papers were on intermediate level. However, there was no study which included intervention blind. Conclusion : Suggested standards that need to be supplemented and discussions on qualitative improvement including repetitive research on the mediation effect during the application of the single subject research methodology, the securement of adequate data sections, and processing of a mediation blind. It is expected to be used as basic data for conducting a better qualitative research in the future.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.137-146
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• 2005

IP-based design methodology has been popularly employed for SoC design to reduce design complexity and to cope with time-to-market pressure. Interface modules for communication between system buses and IPs are required, since many IPs employ different protocols. Automatic generation of these interface modules would enhance designer's productivity and IP's reusability. This paper proposes an automatic interface generation system based on FSM generated from the protocol description of IPs. The proposed system provides the library modules for the standard buses to reduce the burdens of describing the protocols for data transfer from/to standard buses. Experimental results show that the area of the interface circuits generated by the proposed system had been increased slightly by 4.5% on the average when compared to manual designs. In the experiment, where bus clock is 100 Mhz and slave module clock is 34 Mhz, the latency of the interface had been increased by 7.1% in burst mode to transfer 16 data words. However, occupation of system bus can be reduce by 64.9%. A chip designer can generate an interface that improves the efficiency of system bus, by using this system.