• Journal of KIISE:Computer Systems and Theory
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• v.35 no.1
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• pp.30-43
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• 2008

Memory reference instructions such as loads or stores are critical factors that limit the processing power of processor. The prefetching technique is an effective way to reduce the latency caused from memory access. However, excessively aggressive prefetch leads to cache pollution so as to cancel out the advantage of prefetch. In this study, four filtering schemes have been compared and evaluated which dynamically decide whether to begin prefetch after referring a filtering table to decrease cache pollution. First, A bi-states scheme has been shown to analyze the lock problem of the conventional scheme, this scheme such as conventional scheme used to be N:1 mapping, but it has the two state to 1bit value of each entries. A complete state scheme has been introduced to be used as a reference for the comparative study. A block address lookup scheme has been proposed as the main idea of this paper which exhibits the most exact filtering performance. This scheme has a length of the table the same as the bi-states scheme, the contents of each entry have the fields the same as the complete state scheme recently, never referenced data block address has been 1:1 mapping a entry of the filter table. Experimental results from commonly used general benchmarks and multimedia programs show that average cache miss ratio have been decreased by 10.5% for the block address lookup scheme(BAL) compare to conventional dynamic filter scheme(2-bitSC).

• Journal of Broadcast Engineering
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• v.17 no.2
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• pp.374-387
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• 2012

In this paper, we implement a new hardware for finding the significant coefficients of a digital hologram and ciphering them using discrete wavelet packet transform (DWPT). Discrete wavelet transform (DWT) and packetization of subbands is used, and the adopted ciphering technique can encrypt the subbands with various robustness based on the level of the wavelet transform and the threshold of subband energy. The hologram encryption consists of two parts; the first is to process DWPT, and the second is to encrypt the coefficients. We propose a lifting based hardware architecture for fast DWPT and block ciphering system with multi-mode for the various types of encryption. The unit cell which calculates the repeated arithmetic with the same structure is proposed and then it is expanded to the lifting kernel hardware. The block ciphering system is configured with three block cipher, AES, SEED and 3DES and encrypt and decrypt data with minimal latency time(minimum 128 clocks, maximum 256 clock) in real time. The information of a digital hologram can be hided by encrypting 0.032% data of all. The implemented hardware used about 200K gates in $0.25{\mu}m$ CMOS library and was stably operated with 165MHz clock frequency in timing simulation.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.9
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• pp.459-466
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• 2007

TCP/IP processing imposes a heavy load on the host CPU when it is processed by the host CPU on a very high-speed network. Recently the TCP/IP Offload Engine (TOE), which processes TCP/IP on a network adapter instead of the host CPU, has become an attractive solution to reduce the load in the host CPU. There have been two approaches to implement TOE. One is the software TOE in which TCP/IP is processed by an embedded processor and the other is the hardware TOE in which TCP/IP is processed by a dedicated ASIC. The software TOE has poor performance and the hardware TOE is neither flexible nor expandable enough to add new features. In this paper we designed and implemented a hybrid TOE architecture, in which TCP/IP is processed by cooperation of hardware and software, based on an FPGA that has two embedded processor cores. The hybrid TOE can have high performance by processing time-critical operations such as making and processing data packets in hardware. The software based on the embedded Linux performs operations that are not time-critical such as connection establishment, flow control and congestions, thus the hybrid TOE can have enough flexibility and expandability. To improve the performance of the hybrid TOE, we developed a hardware-based transmission/reception accelerator that processes important operations such as creating data packets. In the experiments the hybrid TOE shows the minimum latency of about $19{\mu}s$. The CPU utilization of the hybrid TOE is below 6 % and the maximum bandwidth of the hybrid TOE is about 675 Mbps.

• The korean journal of orthodontics
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• v.21 no.1 s.33
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• pp.197-221
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• 1991

The purpose of the present study was to investigate the differences of EMG activity of the masticatory muscles between normal occlusion and Class III malocclusion during various jaw functions. 46 subjects of 18.4-25.7 years were employed in this study: 26 subjects were normal occlusions, and 20 subjects were Class III malocclusions. The EMG data from the anterior and posterior temporal, anterior and posterior masseter muscles in both sides as mandibular elevators and supra-hyoid muscle group (close to the anterior belly of digastric muscle in right side) as mandibular depressor were recorded with the Medelec MS 25 electromyographic machine. The EMG recordings were analyzed during mandibular rest position, maximal biting, mastication with chewing gum, and swallowing of peanuts. All data were recorded and statistically processed. 1. The maximal mean amplitude of the anterior temporal muscle was stronger significantly in Class III malocclusion than in normal occlusion, and then the posterior temporal was weaker during mandibular rest position. 2. The maximal mean amplitudes in the anterior and posterior temporal muscles and the anterior masseter muscle of Class III malocclusion was weaker significantly than that of normal occlusion during maximal biting. 3. During mastication of the chewing gum, the maximal mean amplitudes of Class III malocclusion was weaker significantly than normal occlusion in the anterior and posterior temporal muscles of the working side, and the duration of Class III malocclusion was longer in the anterior temporal muscles of both aides, and the posterior temporal and the anterior masseter muscle of the balancing side. There were significant increasings of the latency in balancing anterior temporal, working posterior temporal muscles and supra-hyoid muscle group of Class III malocclusion. The silent period durations was 16.36 ms in Class III malocclusion while 10.76 ms in normal occlusion, which was statistically different (P < 0.05). 4. At swallowing of peanuts, the maximal mean amplitude of Class malocclusion was weaker significantly in the posterior temporal muscle than that of normal occlusion. There was no significant difference of duration between normal occlusion and Class III malocclusion. 5 The muscle activities of Class III malocclusion had a tendency of decrease less than normal occlusion. And then the muscle activities of the anterior temporal and anterior masseter muscles in Class III malocclusion showed the tendency of the increase more than other muscles of Class III malocclusion.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.11-20
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• 2014

For Web-based applications in IoT environment, IETF CoRE WG has standardizing the CoAP. One of limitations of CoAP is that CoAP standard does not consider the mobility management of the CoAP sensor node. In this paper, we propose the mobility management protocol of CoAP sensor node by considering the characteristics of the constrained network. The proposed mobility management protocol supports for Web client to be transmitted the sensing data from CoAP node reliably while the CoAP sensor moves into different wireless networks. To do this, we designed the architecture with the separate IP address management of CoAP sensor node and presented the mobility management protocol, which includes the holding and binding mode, in order to provide the reliable transmission. Finally, the numerical analysis and simulation with NS2 tool have been done for the performance evaluation in terms of the handover latency and packet loss with comparing the proposed mobility management protocol with other the existing mobility management protocols. The performance result shows that the proposed mobility management can provide the transmission of sensing data without the packet loss comparing with the existing mobility management protocol reliably.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.3
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• pp.89-101
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• 2014

Recently, as domestic air traffic dramatically increases, the need of ATC(air traffic control) systems has grown for safe and efficient ATM(air traffic management). Especially, for smooth ATC, it is far more important that performance of display system which should show all air traffic situation in FIR(Flight Information Region) without additional latency is guaranteed. In this paper, we design a ASTERIX(All purpose STructured Eurocontrol suRveillance Information eXchange) parsing module to promote stable ATC by minimizing system loads, which is connected with reducing overheads arisen when we parse ASTERIX message. Our ASTERIX parsing module based on pattern matching creates patterns by analyzing received ASTERIX data, and handles following received ASTERIX data using pre-defined procedure through patterns. This module minimizes display errors by rapidly extracting only necessary information for display different from existing parsing module containing unnecessary parsing procedure. Therefore, this designed module is to enable controllers to operate stable ATC. The comparison with existing general bit level ASTERIX parsing module shows that ASTERIX parsing module based on pattern matching has shorter processing delay, higher throughput, and lower CPU usage.

• Journal of the Korea Society of Computer and Information
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• v.16 no.10
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• pp.147-153
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• 2011

In this paper, we present a new video management technique using forward timeline to efficiently store and delete the videos on a local server. The proposed method is based on capturing the changing preference of the videos according to recentness, frequency, and playback length of the requested videos. For this purpose, we utilize the forward timeline which represents the time area within a number of predefined intervals. The local server periodically measures time popularity and request segment of all videos. Based on the measured data, time popularity and request segment, the local server calculates the mean time popularity and mean request segment of a video using forward timeline. Using mean time popularity and mean request segment of video, we estimate the ranking and allocated storage space of a video. The ranking represents the priority of deletion when the storage area of local server is running out of space and the allocated storage space means the maximum size of storage space to be allocated to a video. In addition, we propose an efficient storage space partitioning technique in order to stably store videos and present a time based free-up storage space technique using the expected variation of video data in order for avoiding the overflow on a local server in advance. The simulation results show that the proposed method performs better than other methods in terms of hit rate and number of deletion. Therefore, our video management technique for local server provides the lowest user start-up latency and the highest bandwidth saving significantly.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.8
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• pp.719-729
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• 2000

Prefetching aims at reducing memory latency by fetching, in advance, data that are likely to be requested by the processor in a near future. The effectiveness of prefetching is determined by how accurate the prediction on the needed instructions and data is. Most previous studies on prefetching were limited to proposing a particular prefetch scheme and its performance evaluation, paying little attention to theoretical aspects of prefetching. This paper focuses on the theoretical aspects of instruction prefetching. For this purpose, we propose a clairvoyant prefetch model that makes use of perfect history information. Based on this theoretical model, we analyzed upper limits on the prefetch prediction accuracies of the SPEC benchmarks. The results show that the prefetch prediction accuracy is very high when there is no cache. However, as the size of the instruction cache increases, the prefetch prediction accuracy drops drastically. For example, in the case of the spice benchmark, the prefetch prediction accuracy drops from 53% to 39% when the cache size increases from 2Kbyte to 16Kbyte (assuming 16byte block size). These results indicate that as the cache size increases, most localities are captured by the cache and that instruction prefetching based on the information extracted from the references that missed in the cache suffers from prediction inaccuracies

• Smart Media Journal
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• v.9 no.2
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• pp.16-21
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• 2020

Recently, mobile traffic is increasing exponentially as major traffic is transferred to IoT and visual media data in the dissemination of mobile communication terminals and contents use. In order to overcome the limitations of the existing LTE system, 5G mobile communication technology (5G) is a technology that meets 1000 times data traffic capacity, 4G LTE system acceptance, low latency, high energy efficiency, and high cost compared to 4G LTE system. The path loss due to the use of the frequency domain is very high, so it may be difficult to provide a service compared to the existing 4G LTE system. To overcome these shortcomings, various techniques are under study. In this paper, small cell technology is introduced to improve the system performance of 5G mobile communication systems. The performance is analyzed by comparing the results of small cell technology application, macro communication and small cell communication, and the results of the proposed algorithm application for power control. The analysis results show that the use of small cell technology in the 5th generation mobile communication system can significantly reduce the shadow area and reduce the millimeter wave path loss problem.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11C
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• pp.1077-1087
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• 2003

In this paper, we proposed an architecture of a cryptosystem with various operating modes for the network security and implemented in hardware using the ASIC library. For configuring a cryptosystem, the standard block ciphers such as AES, SEED and 3DES were included. And the implemented cryptosystem can encrypt and decrypt the data in real time through the wired/wireless network with the minimum latency time (minimum 64 clocks, maximum 256 clocks). It can support CTR mode which is widely used recently as well as the conventional block cipher modes such as ECB, CBC and OFB, and operates in the multi-bit mode (64, 128, 192, and 256 bits). The implemented hardware has the expansion possibility for the other algorithms according to the network security protocol such as IPsec and the included ciphering blocks can be operated simultaneously. The self-ciphering mode and various ciphering mode can be supported by the hardware sharing and the programmable data-path. The global operation is programmed by the serial communication port and the operation is decided by the control signals decoded from the instruction by the host. The designed hardware using VHDL was synthesized with Hynix 0.25$\mu\textrm{m}$ CMOS technology and it used the about 100,000 gates. Also we could assure the stable operation in the timing simulation over 100㎒ using NC-verilog.