• Smart Structures and Systems
• /
• v.14 no.6
• /
• pp.1197-1220
• /
• 2014

Accurate actuator tracking is critical to achieve reliable real-time hybrid simulation results for earthquake engineering research. The frequency-domain evaluation approach provides an innovative way for more quantitative post-simulation evaluation of actuator tracking errors compared with existing time domain based techniques. Utilizing the Fast Fourier Transform the approach analyzes the actuator error in terms of amplitude and phrase errors. Existing application of the approach requires using the complete length of the experimental data. To improve the computational efficiency, two techniques including data decimation and frequency decimation are analyzed to reduce the amount of data involved in the frequency-domain evaluation. The presented study aims to enhance the computational efficiency of the approach in order to utilize it for future on-line actuator tracking evaluation. Both computational simulation and laboratory experimental results are analyzed and recommendations on the two decimation factors are provided based on the findings from this study.

• Journal of the Korea Institute of Military Science and Technology
• /
• v.24 no.5
• /
• pp.475-481
• /
• 2021

The on-board processor of satellite Synthetic Aperture Radar(SAR) digitizes the back-scattered echoes and transmits them to the ground. As satellite SAR image of various operating conditions including broadband and high resolution is required, an enormous amount of SAR data is generated. Decimation filter is used for data compression to improve the transmission efficiency of these data. Decimation filter is implemented with the FIR(Finite Impulse Response) filter and here, the decimation ratio and tap length are constrained by resource requirements of FPGA used for implementation. This paper suggests to use a non-integer ratio decimation filter in order to optimize the data transmission efficiency. Also, it proposes a filter design method that remarkably reduces the resource constraints of the FPGA in-use via applying a polyphase filter structure. The required resources for implementing the proposed filter is analysed in this paper.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.5
• /
• pp.16-22
• /
• 2000

This paper presents a compression algorithm applicable for transmitting a HPO hologram data. The proposed algorithm exploits a modulating function to compress the bandwidth of the hologram pattern, resulting in decimation due to relaxed Nyquist sampling constraints. At the receiver, the compressed data will be interpolated and compensated via being divided by the modulating function. We also present compression rate and analyze the resolution of a reconstructed image and the periodicity of harmonic interferences. Finally, we shows the validity of the proposed algorithm by simulation where a reconstructed image from undersampled data is compared with a reconstructed image obtained through decimatioin by modulating function, interpolation and compensation.

• Journal of the Semiconductor & Display Technology
• /
• v.20 no.3
• /
• pp.71-76
• /
• 2021

Digital decimation filters are used in various digital signal processing systems using ADCs, including digital communication systems and sensor network systems. When the sampling rate of digital data is reduced, aliasing occurs. So, an anti-aliasing filter is necessary to suppress aliasing before down-sampling the data. Since the anti-aliasing filter has to have a sharp transition band between the passband and the stopband, the order of the filter is very high. However, as the order of the filter increases, the complexity and area of the filter increase, and more power is consumed. Therefore, in this paper, we propose two types of decimation filters, focusing on reducing the area of the hardware. In both cases, the complexity of the circuit is reduced by applying the required down-sampling rate in two times instead of at once. In addition, CIC decimation filters without a multiplier are used as the decimation filter of the first stage. The second stage is implemented using a CIC filter and a down sampler with an anti-aliasing filter, respectively. It is designed with Verilog-HDL and its function and implementation are validated using ModelSim and Quartus, respectively.

• Journal of information and communication convergence engineering
• /
• v.13 no.4
• /
• pp.235-240
• /
• 2015

A decimation chain for multi-standard reconfigurable radios is presented for 900-MHz and 1,900-MHz dual-band cellular standards with a data interpolator based on the Lagrange method for adjusting the variable data rate to a fixed data rate appropriate for each standard. The two proposed configurations are analyzed and compared to provide insight into aliasing and the signal bandwidth by means of a newly introduced measure called interpolation error. The average interpolation error is reduced as the ratio of the sampling frequency to the signal BW is increased. The decimation chain and the multi-rate analog-to-digital converter are simulated to compute the interpolation error and the output signal-to-noise ratio. Further, a method to operate the above-mentioned chain under a compressed mode of operation is proposed in order to guarantee continuous packet connectivity for inter-radio-access technologies. The presented decimation chain can be applied to LTE, WCDMA, GSM multi-mode multi-band digital front-end which will ultimately lead to the software-defined radio.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.49 no.11
• /
• pp.141-148
• /
• 2012

A design of a 32-bit fourth-stage decimation filter decimation filter used in sigma-delta analog-to-digital (A/D) converter is proposed in this work. A four-stage decimation filter with down-sampling factor of 512 and 32-bit output is developed. A multi-stage cascaded integrator-comb (CIC) filter, which reduces the sampling rate by 64, is used in the first stage. Three half-band FIR filters are used after the CIC filter, each of which reduces the sampling rate by two. The pipeline structure is applied in the CIC filter to reduce the power consumption of the CIC. The Canonic Signed Digit (CSD) arithmetic is used to optimize the multiplier structure of the FIR filter. This filter is implemented based on a semi-custom design flow and a 130nm CMOS standard cell library. This decimation filter operates at 98.304 MHz and provides 32-bit output data at an audio frequency of 192 kHz with power consumption of $697{\mu}W$. In comparison to the previous work, this design shows a higher performance in resolution, operation frequency and decimation factor with lower power consumption and small logic utilization.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.19 no.11
• /
• pp.2649-2655
• /
• 2015

While the oversampling sigma-delta ADCs are known to have high resolution, they often suffer from SNDR losses when operated at a very high data clock. This paper presents a design and implementation of a decimation filter that provides minimum distortion at passband for high-speed sigma-delta ADC. The proposed digital decimation filter employs a butterworth structure. To evaluate the performance of the proposed decimation filter, we implemented a 1-bit, third-order, OSR=64 sigma-delta modulator followed by the proposed decimation filter. Using the simulation ad measurement, we compared the performance of the proposed decimation filter with a conventional CIC(cascaded integrator comb) decimation filter, which is commonly used in most sigma-delta ADCs. The measurement results show that the proposed decimation filter presents substantially lower distortion at passband and thus can provide must higher SNDR.

• Korean Journal of Computational Design and Engineering
• /
• v.5 no.4
• /
• pp.347-358
• /
• 2000

The view dependency of typical spatial-partitioning based NC simulation methods is overcome by polygon rendering technique that generates polygons to represent the workpiece, thus enabling dynamic viewing transformations without reconstruction of the entire data structure. However, the polygon rendering technique still has difficulty in realizing real-time simulation due to unsatisfactory performance of current graphics devices. Therefore, it is necessary to develop a mesh decimation method that enables rapid rendering without loss of display quality. In this paper. we proposed a new mesh decimation algorithm thor a workpiece whose shape varies dynamically. In this algorithm, the 2-map data thor a given workpiece is divided into several regions, and a triangular mesh is constructed for each region first. Then, if any region it cut by the tool, its mesh is regenerated and decimated again. Since the range of mesh decimation is confined to a few regions, the reduced polygons for rendering can be obtained rapidly. Our method enables the polygon-rendering based NC simulation to be applied to the computers equipped with a wider range of graphics cards.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2015.10a
• /
• pp.405-408
• /
• 2015

While the oversampling sigma-delta ADCs are known to have high resolution, they often suffer from SNDR losses when operated at a very high data clock. This paper presents a design and implementation of a decimation filter that provides minimum distortion at passband for high-speed sigma-delta ADC. The proposed digital decimation filter employs a butterworth structure, which is a type of an IIR filter. To evaluate the performance of the proposed decimation filter, we implemented a 1-bit, third-order, OSR=64 sigma-delta modulator followed by the proposed decimation filter. Using the simulation ad measurement, we compared the performance of the proposed decimation filter with a conventional CIC(cascaded integrator comb) decimation filter, which is commonly used in most sigma-delta ADCs. The measurement results show that the proposed decimation filter presents substantially lower distortion at passband and thus can provide must higher SNDR.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.7
• /
• pp.455-463
• /
• 2001

In this Paper, an approximate processing method is proposed and tested. The proposed method uses variable CSD (VCSD) coefficients which approximate filter stopband attenuation by controlling the precision of the CSD coefficient sets. A decimation filter for Audio Codec '97 specifications has been designed having processor architecture that consists of program/data memory, arithmetic unit, energy/level decision, and sinc filter blocks, and fabricated with 0.6${\mu}{\textrm}{m}$ CMOS sea-of-gate technology. For the combined two halfband FIR filters in decimation filter, the number of addition operations were reduced to 63.5%, 35.7%, and 13.9%, compared to worst-case which is not an adaptive one. Experimental results show that the total power reduction rate of the filter is varying from 3.8 % to 9.0 % with respect to worst-case. The proposed approximate processing method using variable CSD coefficients is readily applicable to various kinds of filters and suitable, especially, for the speech and audio applications, like oversampling ADCs and DACs, filter banks, voice/audio codecs, etc.