• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.8
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• pp.1201-1210
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• 1990

This paper proposes on-chip instruction and data cache memories on RISC reduced instruction set computer) architecture which supports fast instruction fetch and data read/write, and enables RISC processor under research to obtain high performance. In the execution of HLL(high level language) programs, heavily used local scalar variables are stored in large register file, but arrays, structures, and global scalar variables are difficult for compiler to allocate registers. These problems can be solved by on-chip Instruction/Data cache. And each cycle of instruction fetch, pad delay causes the lowering of the processors's performance. Cache memories are designed in CMOS technology and SRAM(static-RAM), that saves layout area and power dissipation, is used for instruction and data storage. To speed up and support RISC processor's piplined architecture efficiently, hardwired logic technology is used overall circuits i cache blocks. The schematic capture and timing simulation of proposed cache memorises are performed on Apollo DN4000 workstation using Mentor Graphics CAD tools.

• Journal of the Korea Society of Computer and Information
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• v.18 no.2
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• pp.1-8
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• 2013

TIn this paper, we propose a high performance L1 cache structure on the high clock CPU of 4GHz. The proposed cache memory consists of three parts, i.e., a direct-mapped cache to support fast access time, a two-way set associative buffer to exploit temporal locality, and a buffer-select table. The most recently accessed data is stored in the direct-mapped cache. If a data has a high probability of a repeated reference, when the data is replaced from the direct-mapped cache, the data is selectively stored into the two-way set associative buffer. For the high performance and low power consumption, we propose an one way among two ways set associative buffer is selectively accessed based on the buffer-select table(BST). According to simulation results, Energy $^*$ Delay product can improve about 45%, 70% and 75% compared with a direct mapped cache, a four-way set associative cache, and a victim cache with two times more space respectively.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.11
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• pp.1429-1436
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• 1999

데이타들에 대한 선인출 효과를 얻기 위하여 캐쉬 메모리의 캐쉬 블록은 다중 워드로 구성된다. 그러나 선인출된 데이타들이 사용되지 않을 경우 캐쉬 메모리가 낭비되고 따라서 캐쉬 실패율이 증가한다. 데이타 배열 병합 방법은 캐쉬 실패 원인의 하나인 캐쉬 충돌 실패를 감소시키기 위하여 사용되고 있다. 그러나 기존의 배열 병합 방법은 유용하지 못한 데이타들을 캐쉬 블록에 선인출하는 현상을 보인다. 본 논문에서는 이러한 현상을 개선한 스트라이드 배열 병합을 제안한다. 모의시험에서 캐쉬 블록이 다중 워드로 구성된 경우 스트라이드 배열 병합은 캐쉬 충돌 실패를 감소시킬 뿐 만 아니라 유용한 데이타 선인출을 증가 시키므로 캐쉬 성능을 향상시킴을 보여준다. 또한 이렇게 향상된 캐쉬 성능은 프로세서 증가에 따른 확장성 있는 프로그램 성능을 나타낸다.Abstract The cache memory is composed of cache lines with multiple words to achieve the effect of data prefetching. However, if the prefetched data are not used, the spaces of the cache memory are wasted and thus the cache miss rate increases. The data merging-arrays method is used for the sake of the reduction of the cache conflict misses. However, the existing merging-arrays method results in the useless data prefetching. In this paper, a stride merging-arrays method is suggested for improving this phenomenon. Simulation results show that when a cache line is composed of multiple words, the stride merging-arrays method increases the cache performance due to not only the reduction of cache conflict misses but also the useful data prefetching. This enhanced cache performance also represents the more scalable performance of parallel applications according to increasing the number of processors.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.1
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• pp.1-9
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• 2007

Since data caches used in modern embedded processors consume significant fraction of total processor power up to 40%, embedded processors need power-efficient high performance data caches. This paper proposes a prefetching data cache structure which pursuing low power consumption. We added tag history table on existing data cache structure which includes hardware unit for data prefetching so that reduce the number of parallel lookup on tag memory. This strategic cache structure remarkably reduces power consumption for parallel tag lookup. Experimental results show that the proposed cache architecture induce low power consumption while maintain the same cache performance.

• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.3
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• pp.129-134
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• 2012

The objective of cache is to reduce I/O access of physical storage device so that user accesses their data faster. Traditionally, the most important metric to measure the performance of cache is hitratio. Thus, when the cache maintains hitratio high, it is regarded as a good cache replacement policy. However, the cache miss latency is different when the storages are heterogeneous. Though the cache hitratio is high, if the cache often misses with low performance disk, then the user experiences low performance. To address this problem we proposed eviction cost estimation based cache management. In our result, the eviction cost estimation based cache management has 10~30% throughput improvement compared with LRU cache management.

• The KIPS Transactions:PartA
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• v.15A no.1
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• pp.17-26
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• 2008

This paper proposes an efficient caching mechanism appropriate for the integrated RFID middleware which can integrate wireless sensor networks (WSNs) and RFID (radio frequency identification) systems. The operating environment of the integrated RFID middleware is expected to face the situations of a significant amount of data reading from RFID readers, constant stream data input from large numbers of autonomous sensor nodes, and queries from various applications to history data sensed before and stored in distributed storages. Consequently, an efficient middleware layer equipping with caching mechanism is inevitably necessary for low latency of request-response while processing both data stream from sensor networks and history data from distributed database. For this purpose, the proposed caching mechanism includes two optimization methods to reduce the overhead of data processing in RFID middleware based on the classical cache implementation polices. One is data stream cache (DSC) and the other is history data cache (HDC), according to the structure of data request. We conduct a number of simulation experiments under different parameters and the results show that the proposed caching mechanism contributes considerably to fast request-response times.

• The Journal of the Korea Contents Association
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• v.18 no.3
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• pp.70-80
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• 2018

Due to the recent development of social media and mobile devices, graph data have been using in various fields. In addition, caching techniques for reducing I/O costs in the process of large capacity graph data have been studied. In this paper, we propose a multi-layer caching scheme considering the connectivity of the graph, which is the characteristics of the graph topology, and the history of the past subgraph usage. The proposed scheme divides a cache into Used Data Cache and Prefetched Cache. The Used Data Cache maintains data by weights according to the frequently used sub-graph patterns. The Prefetched Cache maintains the neighbor data of the recently used data that are not used. In order to extract the graph patterns, their past history information is used. Since the frequently used sub-graphs have high probabilities to be reused, they are cached. It uses a strategy to replace new data with less likely data to be used if the memory is full. Through the performance evaluation, we prove that the proposed caching scheme is superior to the existing cache management scheme.

• The Journal of the Korea Contents Association
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• v.14 no.10
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• pp.20-31
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• 2014

Recently, cache sharing methods have been studied in order to effectively reply to user requests in mobile P2P networks. In this paper, we propose a cache sharing scheme based on a cluster considering the peer connectivity in mobile P2P networks. The proposed scheme shares caches by making a cluster that consists of peers preserving the connectivity among them for a long time. The proposed scheme reduces data duplication to efficiently use the cache space in a cluster. The cache space is divided into two parts with a data cache and a temporary cache for a cache space. It is possible to reduce the delay time when the cluster topology is changed or the cache data is replaced utilizing a temporary cache. The proposed scheme checks the caches of peers in a route to a cluster header and the caches of one-hop peers in order to reduce the communication cost. It is shown through performance evaluation that the proposed scheme outperforms the existing schemes.

• The KIPS Transactions:PartA
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• v.14A no.1 s.105
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• pp.55-62
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• 2007

Uptime of embedded processors for mobile devices are dependent on battery consumption. Especially the large portion of power consumption is known to be due to cache management in embedded processors. This paper proposes an energy efficient data cache structure for high performance embedded processors. High performance prefetching data cache issues prefetching instructions before issuing demand-fetch instructions based on reference predictions. These prefetching instruction bring reduction on memory delay by improving cache hit ratio, but on the other hand those increase energy consumption in proportion to the number of prefetching instructions. In this paper, we adopt tag history table on prefetching data cache for reducing energy consumption by minimizing parallel tag comparison. Experimental results show the proposed data cache improves performance on energy consumption as well as memory delay.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.5
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• pp.293-299
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• 2007

Intelligent pipeline inspection gauges (PIGs) are inspection vehicles that move along within a (gas or oil) pipeline and acquire signals (also called sensor data) from their surrounding rings of sensors. By analyzing the signals captured in intelligent PIGs, we can detect pipeline defects, such as holes and curvatures and other potential causes of gas explosions. There are two major data access patterns apparent when an analyzer accesses the pipeline signal data. The first is a sequential pattern where an analyst reads the sensor data one time only in a sequential fashion. The second is the repetitive pattern where an analyzer repeatedly reads the signal data within a fixed range; this is the dominant pattern in analyzing the signal data. The existing PIG software reads signal data directly from the server at every user#s request, requiring network transfer and disk access cost. It works well only for the sequential pattern, but not for the more dominant repetitive pattern. This problem becomes very serious in a client/server environment where several analysts analyze the signal data concurrently. To tackle this problem, we devise a fast in-memory cache manager, called T-Cache, by considering pipeline sensor data as multiple time-series data and by efficiently caching the time-series data at T-Cache. To the best of the authors# knowledge, this is the first research on caching pipeline signals on the client-side. We propose a new concept of the signal cache line as a caching unit, which is a set of time-series signal data for a fixed distance. We also provide the various data structures including smart cursors and algorithms used in T-Cache. Experimental results show that T-Cache performs much better for the repetitive pattern in terms of disk I/Os and the elapsed time. Even with the sequential pattern, T-Cache shows almost the same performance as a system that does not use any caching, indicating the caching overhead in T-Cache is negligible.