• International conference on construction engineering and project management
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• 2013.01a
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• pp.267-273
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• 2013

Early design phase energy modeling is used to provide the design team with first order of magnitude feedback about the impact of various building configurations. For better energy-conscious and sustainable building design and operation, the construction of BIM data interoperability for energy performance assessment in the early design phase is important. The purpose of this study is to suggest construction of BIM data interoperability for energy performance assessment based on BIM. To archive this purpose, the authors have investigated advantage of BIM-based energy performance assessment through comparison with traditional energy performance assessment and suggested requirement for construction of open BIM environment such as BIM data creation, BIM data software practical use, BIM data application and verification. In addition, the authors have suggested BIM data interoperability and BIM energy property mapping method focused on materials.

• Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
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• 2006.11a
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• pp.298-302
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• 2006

As the age of information technology is coming, companies stress the need of knowledge management. Companies construct ERP system including knowledge management. But, it is not easy to formalize knowledge in organization. we focused on data mining system by using genetic programming. But, we don't have enough data to perform the learning process of genetic programming. We have to reduce input parameter(s) or increase number of learning or training data. In order to do this, the enhanced data mining system by using GP combined with SOM(Self organizing map) is adopted in this paper. We can reduce the number of learning data by adopting SOM.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.2
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• pp.444-461
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• 2016

A power-saving mechanism for smartphone devices is developed by analyzing the features of data that are received from Internet of Things (IoT) sensors devices to optimize the data processing policies. In the proposed GreenIoT architecture for power-saving in IoT, the power saving and feedback mechanism are implemented in the IoT middleware. When the GreenIoT application in the power-saving IoT architecture is launched, IoT devices collect the sensor data and send them to the middleware. After the scanning module in the IoT middleware has received the data, the data are analyzed by a feature evaluation module and a threshold analysis module. Based on the analytical results, the policy decision module processes the data in the device or in the cloud computing environment. The feedback mechanism then records the power consumed and, based on the history of these records, dynamically adjusts the threshold value to increase accuracy. Two smart living applications, a biomedical application and a smart building application, are proposed. Comparisons of data processed in the cloud computing environment show that the power-saving mechanism with IoT architecture reduces the power consumed by these applications by 24% and 9.2%.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.11
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• pp.5389-5396
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• 2012

In this paper, an optimized residual data decoder architecture is proposed to improve the performance in H.264/AVC. The proposed architecture is an integrated architecture that combined parallel inverse transform architecture and parallel inverse quantization architecture with common operation units applied new inverse quantization equations. The equations without division operation can reduce execution time and quantity of operation for inverse quantization process. The common operation unit uses multiplier and left shifter for the equations. The inverse quantization architecture with four common operation units can reduce execution cycle of inverse quantization to one cycle. The inverse transform architecture consists of eight inverse transform operation units. Therefore, the architecture can reduce the execution cycle of inverse transform to one cycle. Because inverse quantization operation and inverse transform operation are concurrency, the execution cycle of inverse transform and inverse quantization operation for one $4{\times}4$ block is one cycle. The proposed architecture is synthesized using Magnachip 0.18um CMOS technology. The gate count and the critical path delay of the architecture are 21.9k and 5.5ns, respectively. The throughput of the architecture can achieve 2.89Gpixels/sec at the maximum clock frequency of 181MHz. As the result of measuring the performance of the proposed architecture using the extracted data from JM 9.4, the execution cycle of the proposed architecture is about 88.5% less than that of the existing designs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.74-86
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• 2002

This paper proposes a VLSI architecture for high-speed data processing of the differential phase detectors with the decision feedback. To improve the BER performance of the conventional differential phase detection, DF-DPD, DPD-RGPR and DFDPD-SA have been proposed. These detection methods have the architecture feedbacking the detected phase to reduce the noise of the previous symbol as phase reference. However, the feedback of the detected phase results in lower data processing speed than that of the conventional differential phase detection. In this paper, the VLSI architecture was proposed for high-speed data processing of the differential phase detectors with decision feedback. The Proposed architecture has the pre-calculation method to previously calculate the results on 'N'th step at 'M-1'th step and the pre-decision feedback method to previously feedback the predicted phases at 'M-1'th step. The architecture proposed in this paper was implemented to RTL using VHDL. The simulation results show that the Proposed architecture obtains the high-speed data processing.

• Proceedings of the Acoustical Society of Korea Conference
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• 1991.06a
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• pp.163-168
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• 1991

In this paper, we propose a new systolic architecture for the order statistics(OS) constant false alarm rate(CFAR) processor. In the proposed architecture, each processing element(PE) can compare two reference data cells with one test cell simultaneously in each clock cycle. So the utilization of each PE in this architecture is 100% whereas the utilization of each PE in the systolic architecture previously reported by Ritcey and Hwang is 50% because of one clock delay between two adjacent PE's active in computation. This can speed up the data processing rate by a factor of two. With this architecture, we can obtain the reduced number of communication links between adjacent PE's and reduction of the latency by half in comparison with the one proposed by Ritcey and Hwang.

• International Journal of Naval Architecture and Ocean Engineering
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• v.8 no.5
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• pp.496-510
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• 2016

Simulation technology is a type of shipbuilding product lifecycle management solution used to support production planning or decision-making. Normally, most shipbuilding processes are consisted of job shop production, and the modeling and simulation require professional skills and experience on shipbuilding. For these reasons, many shipbuilding companies have difficulties adapting simulation systems, regardless of the necessity for the technology. In this paper, the data model for shipyard production simulation model generation was defined by analyzing the iterative simulation modeling procedure. The shipyard production simulation data model defined in this study contains the information necessary for the conventional simulation modeling procedure and can serve as a basis for simulation model generation. The efficacy of the developed system was validated by applying it to the simulation model generation of the panel block production line. By implementing the initial simulation model generation process, which was performed in the past with a simulation modeler, the proposed system substantially reduced the modeling time. In addition, by reducing the difficulties posed by different modeler-dependent generation methods, the proposed system makes the standardization of the simulation model quality possible.

• Journal of the Society of Naval Architects of Korea
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• v.50 no.5
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• pp.314-323
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• 2013

Production simulation technology is beneficial to solve the complicated and fluctuated problems in a shipyard. It takes too much time and effort to build simulation models in the field, though. This research proposes a feasible method to reduce the difficulties related to simulation modeling for the factory or shop capacity analysis. In addition, a proposed neutral data format for production information is efficient to manage information acquisition for simulation modeling automation. A panel block shop model is contributed to comparison between the conventional technique and the automated one. The automation technique is highly recommended to run a rapid simulation in the shipyard problem.

• The Transactions of the Korea Information Processing Society
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• v.6 no.5
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• pp.1225-1240
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• 1999

This paper proposes PASC(PArtitioned SCHeduler) processor architecture that equips with a number of functional unit and an individual scheduler paris. Every scheduler of the PASC processor can determine whether a unit instruction can be issued to the associated functional unit or it is to be waited until next cycle caused by a resource collision or data dependencies. In the PASC processor, only the functional unit with a resource collision or data dependencies waits by executing a NOP(No OPeration) instruction and the other functional units execute their own instructions. Therefore we can expect the code compaction effect on the PASC processor. Thus, the last instruction of a loop at certain iteration and the very first instruction of the loop at the next iteration can be scheduled simultaneously if the two instructions do not incur any resource collision or data dependencies. Therefore, we can expect that such two instructions without any resource collision and data dependencies are packed into the same very long instruction word and thus, the two instructions are executed concurrently at run time. As a result, we can shorten execution cycles of a loop comparing to the execution of the loop on a traditional VLIW or SVLIW processor architecture. Simulation result also promises faster execution of loops on a PASC processor architecture than those on a VLIW and SVLIW processor architecture.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.3
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• pp.1-10
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• 1997

We present an approach to high-level synthesis for a specific target architecture-partitioned bus architecture. In this approach, we have specific goals of minimizing data transfer length and number of buses in addition to common synthesis goals such as minimizing number of control steps and satisfying given resource constraint. Minimizing data transfer length and number of buses can be very important design goals in the era of deep submicron technology in which interconnection delay and area dominate total delay and area of the chip to be designed. in partitioned bus architecture, to get optimal solution satisfying all the goals, partitioning of operation nodes among segments and ordering of segments as well as scheduling and allocation/binding must be considered concurrently. Those additional goals may impose much more complexity on the existing high-level synthesis problem. To cope with this increased complexity and get reasonable results, we have employed two ideas in ur synthesis approach-extension of the target architecture to alleviate bus requirement for data transfer and adoption of genetic algorithm as a principal methodology for design space exploration. Experimental results show that our approach is a promising high-level synthesis mehtodology for partitioned bus architecture.