• Proceedings of the KIEE Conference
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• 1999.11b
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• pp.364-368
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• 1999

This paper suggests switching regulator technique to overcome the drawback of conventional variable linear power supply. Switching regulator technique can eliminate the extremely lossy operation and reduce the size and weight of variable linear power supply and provide nearly constant output power over the majority of output voltage range. The topology of variable switched mode power supply is employed active clamp forward converter with a current doubler rectifier and by using control of variable-frequency together with control of fixed-frequency, output voltage can be controled. Equivalent circuits pertinent to each operational mode of converter are derived, and an experimental 20V, 50A converter was designed and built. The converter operates from an output voltage of zero to 25 V, under 100 kHz switching frequency.

• ETRI Journal
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• v.44 no.5
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• pp.759-768
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• 2022

A novel energy harvesting technique that uses conducted electromagnetic interference as an energy source is presented. Conducted EMI generated from fluorescent light using a switched-mode power supply was measured and modeled as an equivalent voltage source. Two types of rectifier circuits-a bridge rectifier and a voltage doubler-were used as the harvesting devices for conducted EMI source. The matching networks were designed based on the equivalent model, and the harvested power was improved. The implemented energy harvester produces a regulated power over 68.9 mW and current over 15.1 mA while a regulated voltage can be selected between 3.3 V and 5 V. The proposed system shows the highest harvesting power indoor environment and can provide enough power for the Internet of Things devices.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.838-841
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• 2012

To avoid the damage to circuit and performance degradation by temperature changes, temperature sensing circuit applicable to the IC is proposed in this paper. Temperature sensing is executed by PTAT circuit and power saving mode is activated by internal switch if internal temperature is in high. Also, characteristics of current matching are increased by using current mirror and cascode circuits. From the simulation results, this circuit is operating in action mode if input signal is in low. But it immediately goes into power saving mode if output signal is in high. It shows the output voltage of 1V at $75^{\circ}C$ and 1.75V at $125^{\circ}C$ in action mode and near 0 V(0V~ 7uV) in power saving mode.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.565-566
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• 2008

The high efficiency power management IC(PMIC) for Moblie application is proposed in this paper. PMIC is controlled with PWM control method in order to have high power efficiency at high current level. The saw-tooth generator is made to have 1.2 MHz oscillation frequency and full range of output swing from ground to supply voltage(VDD:3.3V). The comparator is designed with two stage OP amplifier. And the error amplifier has 70dB DC gain and $64^{\circ}$ phase margin. DC-DC converter, based on Voltage-mode PWM control circuits, achieved the high efficiency near 95% at 100mA output current. DC-DC converter is designed with LDO in stand-by mode which fewer than 1mA for high efficiency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.1
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• pp.68-79
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• 1992

In the high speed analog system satellite communication system, video signal processing and optical fiber interface circuits, GaAs high gain operational amplifier is advantageous due to obtain a high gain because of its low transconductance and other drawbacks, such as low frequency dispersion and process variation. Therefore in this paper, a circuit techniques for improving the voltage gain for GaAs MESFET amplifier is presented. Also, various types of existing current mirror and current mirror proposed are compared.To obtain the high differential gain, bootstrap gain enhancement technique is used and common mode feedback is employed in differential amplifier.The simulation results show that gain is higher than that of basic amplifier about 18.6dB, and stability and frequency performance of differential amplifier are much improved.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.12
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• pp.1730-1736
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• 2015

This paper presents a 16-channel transimpedance amplifier (TIA) array implemented in a standard $0.18-{\mu}m$ CMOS technology for the applications of panoramic scan LADAR (PSL) systems. Since this array is the front-end circuits of the PSL systems to recover three dimensional image for unmanned vehicles, low-noise and high-gain characteristics are necessary. Thus, we propose a voltage-mode inverter TIA (I-TIA) array in this paper, of which measured results demonstrate that each channel of the array achieves $82-dB{\Omega}$ transimpedance gain, 565-MHz bandwidth for 0.5-pF photodiode capacitance, 6.7-pA/sqrt(Hz) noise current spectral density, and 33.8-mW power dissipation from a single 1.8-V supply. The measured eye-diagrams of the array confirm wide and clear eye-openings up to 1.3-Gb/s operations. Also, the optical pulse measurements estimate that the proposed 16-channel TIA array chip can detect signals within 20 meters away from the laser source. The whole chip occupies the area of $5.0{\times}1.1mm^2$ including I/O pads. For comparison, a current-mode 16-channel TIA array is also realized in the same $0.18-{\mu}m$ CMOS technology, which exploits regulated-cascode (RGC) input configuration. Measurements reveal that the I-TIA array achieves superior performance in optical pulse measurements.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.11
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• pp.2100-2106
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• 2007

Multi-stage folding A/D converter circuit with $0.25{\mu}m$ N-well CMOS technology is designed. This A/D converter consists of a transconductance circuit, linear folder circuit and 1bit A/D converter circuit. In H-spice simulation results, linear folder circuits having high linearity can be obtained when the current mode is used instead of voltage mode. And in case of 6bit, the delay time is limited about 40ns. From this results, 6bit 25MSPS A/D converter circuit can be realized.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.10
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• pp.40-47
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• 2016

In this paper, a dual mode buck converter with an ability to change mode is proposed, which is suitable particularly for portable device. The problem of conventional mode control circuit is affected by load variation condition such as suddenly or slowly. To resolve this problem, the mode control was designed with slow clock method. Also, when change from the PFM(Pulse Frequency Modulation) mode to the PWM(Pulse Width Modulation) mode, to use the counter to detect a high load. And the user can select mode transition point in load range from 20mA to 90mA by 3 bit digital signal. The circuits are implemented by using BCDMOS 0.18um 2-polt 3-metal process. Measurement environment are input voltage 3.7V, output voltage 1.2V and load current range from 10uA to 500mA. And measurement result show that the peak efficiency is 86% and ripple voltage is less 32mV.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.2
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• pp.159-164
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• 2016

A wireless communication system is required to be implemented with the low power circuits because it uses a battery having a limited energy. Therefore, the current mode circuit has been studied because it consumes constant power regardless of the frequency change. However, the clock-feedthrough problem is happened by leak of stored energy in memory operation. In this paper, we suggest the current memory circuit to minimize the clock-feedthrough problem and introduce a technique for ultra low power operation by inducing dynamic voltage scaling. The current memory circuit was designed with BSIM3 model of $0.35{\mu}m$ process and was operated in the near-threshold region. From the simulation result, the clock-feedthrough could be minimized when designing the memory MOS Width of $2{\mu}m$, the switch MOS Width of $0.3{\mu}m$ and dummy MOS Width of $13{\mu}m$ in 1MHz switching operation. The power consumption was calculated with $3.7{\mu}W$ at the supply voltage of 1.2 V, near-threshold voltage.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.11
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• pp.36-43
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• 2015

A pixel-level readout circuit is studied for 2-dimensional microbolometer focal plane arrays (FPAs). A current mirroring injection (CMI) input circuit with 2-step current-mode bias suppression is proposed for a pixel-level architecture with high responsivity and long integration time. The proposed circuit has been designed using a $0.35-{\mu}m$ 2-poly 4-metal CMOS process for a $320{\times}240$ microbolometer array with a pixel size of $50{\mu}m{\times}50{\mu}m$. The proposed 2-step bias-current suppression has sufficiently low calibration error with wide calibration range, and the calibration range and error can be easily optimized by controlling some design parameters. Due to high responsivity and a long integration time of more than 1 ms, the noise equivalent temperature difference (NETD) of the proposed circuit can be improved to 26 mK, which is much better than that of the conventional circuits, 67 mK.