• 전기전자학회논문지
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• 제22권3호
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• pp.862-865
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• 2018

The proposed scheme minimizes the Idle time under the residual energy of the sensor node to adjust the Sleep-Wakeup period and minimize unnecessary energy consumption. It is The proposed scheme minimizes the Idle time under the residual energy of the sensor node to adjust the Sleep-Wakeup period and minimize unnecessary energy consumption. It is an important process to control the Application Packet Framework including the PHY and the MAC layer at each node's Idle time with the Idle time mechanism state before the proposed function is executed. The Current Control Level of the Report Attribute is fixed at one sending / receiving node where power consumption can occur, by changing Sleep-Wakeup time, the low power consumption efficiency was improved while satisfying the transmission requirement of the given delay time constraint.

• ETRI Journal
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• 제36권5호
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• pp.876-879
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• 2014

In current NAND flash design, one of the most challenging issues is reducing peak current consumption (peak ICC), as it leads to peak power drop, which can cause malfunctions in NAND flash memory. This paper presents an efficient approach for reducing the peak ICC of the cache program in NAND flash memory - namely, a program Cache Busy Time (tPCBSY) control method. The proposed tPCBSY control method is based on the interesting observation that the array program current (ICC2) is mainly decided by the bit-line bias condition. In the proposed approach, when peak ICC2 becomes larger than a threshold value, which is determined by a cache loop number, cache data cannot be loaded to the cache buffer (CB). On the other hand, when peak ICC2 is smaller than the threshold level, cache data can be loaded to the CB. As a result, the peak ICC of the cache program is reduced by 32% at the least significant bit page and by 15% at the most significant bit page. In addition, the program throughput reaches 20 MB/s in multiplane cache program operation, without restrictions caused by a drop in peak power due to cache program operations in a solid-state drive.

• Journal of Power Electronics
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• 제15권6호
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• pp.1480-1488
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• 2015

In this paper, a revolutionary buck converter is proposed with soft-switching technology, which is realized by a coupled inductor. Both zero-voltage switching (ZVS) of main switch and zero-current switching (ZCS) of freewheeling diode are achieved at turn on and turn off without using any auxiliary circuits by the resonance between the parasitic capacitor and the coupled inductor. Furthermore, the peak voltages of the main switch and the peak current of the freewheeling diode are significantly reduced by the coupled inductor. As a result, the proposed converter has the advantages of simple circuit, convenient control, low consumption and so on. The detailed operation principles and steady-state analysis of the proposed ZVS-ZCS buck converter are presented, and detailed power loss analysis and some simulation results are also included. Finally, experimental results based on a 200-W prototype are provided to verify the theory and design of the proposed converter.

• Nutritional Sciences
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• 제7권3호
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• pp.158-164
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• 2004

This study was conducted to define dietary patterns and to evaluate the effects of socioeconomic, acculturation and lifestyle factors on dietary patterns among 2,746 Korean- Americans in California. It was a cross-sectional telephone survey based on a representative sampling of individuals with a Korean surname using residential phone listings. It was conducted using a food frequency questionnaire that covered 20 food items, socioeconomic variables such as age, gender, income, education and acculturation, and lifestyle factors such as body weight, alcohol consumption, smoking, exercise and consumption of fast food. Four dietary patterns were identified: American Foods (AF), American Breakfast (AB), Korean Foods (KF) and Vegetables (Ⅴ). AF was associated with younger men, acculturation and fast food consumption. AB was associated with women, higher education, current smoking and fast food consumption. KF was associated with acculturation and lower socioeconomic status. Ⅴ was associated with lifestyle factors such as smoking, exercising and fast food consumption. The results of the study showed that socioeconomic and lifestyle factors influenced the dietary patterns of Korean- Americans. This should be considered when dietary interventions are designed for Korean-Americans to improve their health status.

• 대한전자공학회논문지SD
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• 제46권10호
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• pp.53-60
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• 2009

반도체 공정의 발달로 집적도가 증가하고 문턱전압이 감소하면서, 반도체 집적회로 소모 전력에서 누설전류(leakage current)의 비중이 점차 증가하고 있다. 대기 상태에서 CMOS 조합 회로(combinational circuit)는 입력 값에 따라 누설전류가 크게 달라진다. 본 연구에서는 누설전류로 인한 소모전력을 줄이기 위해 대기 상태 (standby state) 회로의 입력 신호를 제어하며, 작은 누설전류를 갖는 입력 신호를 찾기 위한 새로운 효율적인 알고리즘을 개발하였다. 이 방법을 벤치마크 예제에 실험적으로 적용하여 누설전류 평균값에 비해 15.7%, simulated evolution 방법에 비해 6.7% 누설전류를 줄일 수 있음을 보였다. 또한 순차 회로에서도 idle 입력을 이용하여 누설전류 평균값에 비해 6.8%, simulated evolution 방법에 비해 3.2% 누설전류를 줄일 수 있었다.

• 에너지공학
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• 제26권4호
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• pp.127-142
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• 2017

2014.7월 유연탄 개별소비세 부과 이후 고열량탄 및 기준 구간내 상위 열량탄 선호 현상 등 사용량 왜곡 현상이 나타나 평균 도입열량 상승으로 추가적인 연료도입 비용이 발생하였다. 이에 따라 고열량탄 위주의 호주/러시아탄 비중이 확대된 반면 중,저열량탄 위주의 인도네시아탄 비중이 축소되었다. 이는 유연탄의 특성 반영이 미흡한 과세 제도에 따라 나타난 현상으로 사용량 왜곡 뿐 아니라 해외자원 개발 동기부여 저해, 연소기술 개발 차질 등의 문제가 있어 이를 해결 하기 위한 개선 방안이 필요할 것이다. 적정 세수를 유지하면서 사용량 왜곡을 해소할 수 있는 개선방안으로 5,000kcal/kg 기준열량 비례 부과방식과 5,000kcal/kg 기준 열량 세액단가와 동일한 상하 200kcal/kg 단위 총 15 구간 세분화 부과방식이 있으며 이를 통해 사용량 왜곡 현상 해소는 물론 세수증대와 연료도입 비용 절감의 효과가 있을 것으로 예상한다.

• 한국태양에너지학회:학술대회논문집
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• 한국태양에너지학회 2009년도 추계학술발표대회 논문집
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• pp.175-180
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• 2009

Today, the amount of energy consumption at the university campuses is huge. The effort for the energy consumption reduction in university campuses is certainly needed by the following reason; first, contribution for the reduction request about green house gas emission. Second, energy cost reduction in university campus. Third, emotional spreading influence consideration as the maximum higher educational institutions. For the energy consumption reduction in university campus, the energy consumption analysis of current situation has to be executed. The energy reduction possibility in which it exists in university campus can be understood through the energy consumption analysis. And the application is possible as fundamental data of the policy establishment for the effective energy reduction in university campuses. This research analyzed the energy consumption present state of the major university campus of the Korea as the fundamental research for the energy consumption reduction plan preparation of the university campus. Moreover, surveys were performed and analyzed for the energy manager in charge of the university campus.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.211-214
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• 2009

In this paper we will outline the opportunities for flexible OLED devices, both for display and solid-state lighting applications. We will present our recent data, and discuss future challenges, for low power consumption phosphorescent OLED technology fabricated on flexible substrates to enable a new generation of energy efficient electronic devices.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.736-744
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• 2016

Network on chip (NoC) is an emerging technology in the field of multi core interconnection architecture. The routers plays an essential components of Network on chip and responsible for packet delivery by selecting shortest path between source and destination. State-of-the-art NoC designs used routing table to find the shortest path and supports four ports for packet transfer, which consume high power consumption and degrades the system performance. In this paper, the multi port multi core router architecture is proposed to reduce the power consumption and increasing the throughput of the system. The shared buffer is employed between the multi ports of the router architecture. The performance of the proposed router is analyzed in terms of power and current consumption with conventional methods. The proposed system uses Modelsim software for simulation purposes and Xilinx Project Navigator for synthesis purposes. The proposed architecture consumes 31 mW on CPLD XC2C64A processor.

• 한국분무공학회지
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• 제29권1호
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• pp.1-6
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• 2024

This paper is a numerical analysis study for evaluating the energy efficiency of electric vehicles. Currently, the methods for testing and evaluating the energy consumption efficiency of electric vehicles have limitations such as resources and time. Therefore, there is a need for research on developing models to predict the energy consumption efficiency of electric vehicles. In this study, a numerical analysis research is conducted to predict the energy efficiency of electric vehicles using a vehicle dynamics numerical analysis model. To validate the accuracy of the simulation model, it is compared the results of dynamometer tests with the simulation results and used the Unified Diagnostic Services (UDS) protocol to acquire internal data from the electric vehicle. It is ensured the reliability of the simulation model by comparing data such as motor speed, battery voltage, current, state of charge (SOC), regenerative braking power generation, and total driving distance of the test vehicle with dynamometer test data and simulation model results.