• 제목/요약/키워드: cu metallization

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고효율, 저가화 태양전지에 적합한 Ni/Cu 금속 전극 간격에 따른 특성 평가 (Investigation of the Ni/Cu metal grid space for high-effiency, low cost crystlline silicon solar cells)

  • 김민정;이지훈;조경연;이수홍
    • 한국태양에너지학회:학술대회논문집
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    • 한국태양에너지학회 2009년도 춘계학술발표대회 논문집
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    • pp.225-229
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    • 2009
  • The front metal contact is one of the most important element influences in efficiency in the silicon solar cell. First of all selective of the material and formation method is important in metal contacts. Commercial solar cells with screen-printed contacts formed by using Ag paste process is simple relatively and mass production is easy. But it suffer from a low fill factor and a high shading loss because of high contact resistance. Besides Ag paste too expensive. because of depends income. This paper applied for Ni/Cu metallization replace for paste of screen printing front metal contact. Low cost Ni and Cu metal contacts have been formed by using electroless plating and electroplating techniques to replace the screen-printed Ag contacts. Ni has been proposed as a suitable silicide for the salicidation process and is expected to replace conventional silicides. Copper is a promising material for the electrical contacts in solar cells in terms of conductivity and cost. In experiments Ni/Cu metal contact applied same grid formation of screen-printed solar cell. And it has variation of different grid spacing. It was verified that the wide spacing of grid finger could increase the series resistance also the narrow spacing of grid finger also implies a grid with a higher density of grid fingers. Through different grid spacing found alteration of efficiency.

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첨단 반도체 패키징을 위한 미세 피치 Cu Pillar Bump 연구 동향 (Recent Advances in Fine Pitch Cu Pillar Bumps for Advanced Semiconductor Packaging)

  • 노은채;이효원;윤정원
    • 마이크로전자및패키징학회지
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    • 제30권3호
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    • pp.1-10
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    • 2023
  • 최근, 고사양 컴퓨터, 모바일 제품의 수요가 증가하면서 반도체 패키지의 고집적화, 고밀도화가 요구된다. 따라서 많은 양의 데이터를 한 번에 전송하기 위해 범프 크기 및 피치 (Pitch)를 줄이고 I/O 밀도를 증가시킬 수 있는 플립 칩 (flip-chip), 구리 필러 (Cu pillar)와 같은 마이크로 범프 (Micro-bump)가 사용된다. 하지만 범프의 직경이 70 ㎛ 이하일 경우 솔더 (Solder) 내 금속간화합물 (Intermetallic compound, IMC)이 차지하는 부피 분율의 급격한 증가로 인해 취성이 증가하고, 전기적 특성이 감소하여 접합부 신뢰성을 악화시킨다. 따라서 이러한 점을 개선하기 위해 UBM (Under Bump Metallization) 또는 Cu pillar와 솔더 캡 사이에 diffusion barrier 역할을 하는 층을 삽입시키기도 한다. 본 review 논문에서는 추가적인 층 삽입을 통해 마이크로 범프의 과도한 IMC의 성장을 억제하여 접합부 특성을 향상시키기 위한 다양한 연구를 비교 분석하였다.

불순물을 주입한 텅스텐(W) 박막의 확산방지 특성과 박막의 물성 특성연구 (Characteristics and Physical Property of Tungsten(W) Related Diffusion Barrier Added Impurities)

  • 김수인;이창우
    • 한국진공학회지
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    • 제17권6호
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    • pp.518-522
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    • 2008
  • 반도체 집적도의 비약적인 발전으로 박막은 더욱 다층화 되고 선폭은 더욱 미세화가 진행되었다. 이러한 악조건에서 소자의 집적도를 계속 향상시키기 위하여 많은 연구가 진행되고 있다. 특히 소자 집적도 향상으로 금속 배선 공정에서는 선폭의 미세화와 배선 길이 증가로 인한 RC지연이 발생하게 되었다. 이를 방지하기 위하여 Al보다 비저항이 작은 Cu를 배선물질로 사용하여야 하며, 또한 일부 공정에서는 이미 사용하고 있다. 그러나 Cu를 금속배선으로 사용하기 위해 해결해야 할 가장 큰 문제점은 저온에서 쉽게 Si기판과 반응하는 문제이다. 현재까지 본 실험실에서는 tungsten (W)을 주 물질로 W-C-N (tungsten- carbon - nitrogen) 확산방지막을 증착하여 연구를 하였으며, $\beta$-ray, XRD, XPS 분석을 통하여 고온에서도 Cu의 확산을 효과적으로 방지한다는 연구 결과를 얻었다. 이 연구에서는 기존 연구에 추가적으로 W-C-N 확산방지막의 표면을 Nano-Indenter System을 이용하여 확산방지막 표면강도 변화를 분석하여 확산방지막의 물성 특성을 연구하였다. 이러한 연구를 통하여 박막내 불순물인 질소가 포함된 박막이 고온 열처리 과정에서 보다 안정적인 표면강도 변화를 나타내는 연구 결과를 얻었으며, 이로부터 박막의 물성 분석을 실시하였다.

전해도금에 의한 플립칩용 Sn-Cu 솔더범프의 특성에 관한 연구 (A Study on the Characteristics of Sn-Cu Solder Bump for Flip Chip by Electroplating)

  • 정석원;황현;정재필;강춘식
    • 한국마이크로전자및패키징학회:학술대회논문집
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    • 한국마이크로전자및패키징학회 2002년도 추계기술심포지움논문집
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    • pp.49-53
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    • 2002
  • The Sn-Cu eutectic solder bump formation ($140{\mu}{\textrm}{m}$ diameter, $250{\mu}{\textrm}{m}$ pitch) by electroplating was studied for flip chip package fabrication. The effect of current density and plating time on Sn-Cu deposit was investigated. The morphology and composition of plated solder surface was examined by scanning electron microscopy. The plating thickness increased with increasing time. The plating rate increased generally according to current density. After the characteristics of Sn-Cu plating were investigated, Sn-Cu solder bumps were fabricated on optimal condition of 5A/dm$^2$, 2hrs. Ball shear test after reflow was performed to measure adhesion strength between solder bump and UBM (Under Bump Metallization). The shear strength of Sn-Cu bump after reflow was higher than that of before reflow.

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A bilayer diffusion barrier of atomic layer deposited (ALD)-Ru/ALD-TaCN for direct plating of Cu

  • Kim, Soo-Hyun;Yim, Sung-Soo;Lee, Do-Joong;Kim, Ki-Su;Kim, Hyun-Mi;Kim, Ki-Bum;Sohn, Hyun-Chul
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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    • pp.239-240
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    • 2008
  • As semiconductor devices are scaled down for better performance and more functionality, the Cu-based interconnects suffer from the increase of the resistivity of the Cu wires. The resistivity increase, which is attributed to the electron scattering from grain boundaries and interfaces, needs to be addressed in order to further scale down semiconductor devices [1]. The increase in the resistivity of the interconnect can be alleviated by increasing the grain size of electroplating (EP)-Cu or by modifying the Cu surface [1]. Another possible solution is to maximize the portion of the EP-Cu volume in the vias or damascene structures with the conformal diffusion barrier and seed layer by optimizing their deposition processes during Cu interconnect fabrication, which are currently ionized physical vapor deposition (IPVD)-based Ta/TaN bilayer and IPVD-Cu, respectively. The use of in-situ etching, during IPVD of the barrier or the seed layer, has been effective in enlarging the trench volume where the Cu is filled, resulting in improved reliability and performance of the Cu-based interconnect. However, the application of IPVD technology is expected to be limited eventually because of poor sidewall step coverage and the narrow top part of the damascene structures. Recently, Ru has been suggested as a diffusion barrier that is compatible with the direct plating of Cu [2-3]. A single-layer diffusion barrier for the direct plating of Cu is desirable to optimize the resistance of the Cu interconnects because it eliminates the Cu-seed layer. However, previous studies have shown that the Ru by itself is not a suitable diffusion barrier for Cu metallization [4-6]. Thus, the diffusion barrier performance of the Ru film should be improved in order for it to be successfully incorporated as a seed layer/barrier layer for the direct plating of Cu. The improvement of its barrier performance, by modifying the Ru microstructure from columnar to amorphous (by incorporating the N into Ru during PVD), has been previously reported [7]. Another approach for improving the barrier performance of the Ru film is to use Ru as a just seed layer and combine it with superior materials to function as a diffusion barrier against the Cu. A RulTaN bilayer prepared by PVD has recently been suggested as a seed layer/diffusion barrier for Cu. This bilayer was stable between the Cu and Si after annealing at $700^{\circ}C$ for I min [8]. Although these reports dealt with the possible applications of Ru for Cu metallization, cases where the Ru film was prepared by atomic layer deposition (ALD) have not been identified. These are important because of ALD's excellent conformality. In this study, a bilayer diffusion barrier of Ru/TaCN prepared by ALD was investigated. As the addition of the third element into the transition metal nitride disrupts the crystal lattice and leads to the formation of a stable ternary amorphous material, as indicated by Nicolet [9], ALD-TaCN is expected to improve the diffusion barrier performance of the ALD-Ru against Cu. Ru was deposited by a sequential supply of bis(ethylcyclopentadienyl)ruthenium [Ru$(EtCp)_2$] and $NH_3$plasma and TaCN by a sequential supply of $(NEt_2)_3Ta=Nbu^t$ (tert-butylimido-trisdiethylamido-tantalum, TBTDET) and $H_2$ plasma. Sheet resistance measurements, X-ray diffractometry (XRD), and Auger electron spectroscopy (AES) analysis showed that the bilayer diffusion barriers of ALD-Ru (12 nm)/ALD-TaCN (2 nm) and ALD-Ru (4nm)/ALD-TaCN (2 nm) prevented the Cu diffusion up to annealing temperatures of 600 and $550^{\circ}C$ for 30 min, respectively. This is found to be due to the excellent diffusion barrier performance of the ALD-TaCN film against the Cu, due to it having an amorphous structure. A 5-nm-thick ALD-TaCN film was even stable up to annealing at $650^{\circ}C$ between Cu and Si. Transmission electron microscopy (TEM) investigation combined with energy dispersive spectroscopy (EDS) analysis revealed that the ALD-Ru/ALD-TaCN diffusion barrier failed by the Cu diffusion through the bilayer into the Si substrate. This is due to the ALD-TaCN interlayer preventing the interfacial reaction between the Ru and Si.

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Cu 금속배선을 위한 Molybdenum Nitride 확산 방지막 특성 (Characteristics of Molybdenum Nitride Diffusion Barrier for Copper Metallization)

  • 이정엽;박종완
    • 한국재료학회지
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    • 제6권6호
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    • pp.626-631
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    • 1996
  • Reactive dc magnetron sputtering 법을 이용하여 증착한 molybdenum mitride 박막의 Cu 확산 방지막 특성을 조사하였다. Cu 확산 방지막으로서 molybdenum nitride 박막의 열적안정성을 관찰하기 위하여 molybdenum nitride 박막 위에 Cu를 evaporation 법으로 증착하고 진공 열처리하였다. Cu/r-Mo2N/si 구조는 $600^{\circ}C$, 30분간 열처리 시까지 안정하였다. 확산 방지막의 파괴는 $650^{\circ}C$, 30분간 열처리 시부터 격자 확산(lattice diffusion)이나 입계(grain boundary)과 결함(defect)을 통한 확산에 의해 나타나기 시작하였고, 이 때 molybdenum silicide과 copper silicide의 형성에 기인된 것으로 생각되었다. 열처리 이후 Cu/r-Mo2N/Si 사이의 상호반응이 증가하였다. 이는 Rutherford backscattering spectrometry, Auger electron spectroscopy 그리고 Nomarski microscopy 등의 분석을 통해 조사되었다.

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차세대 공정에 적용 가능한 Cu(B)/Ti/SiO2/Si 구조 연구 (A Study on Cu(B)/Ti/SiO2/Si Structure for Application to Advanced Manufacturing Process)

  • 이섭;이재갑
    • 한국재료학회지
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    • 제14권4호
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    • pp.246-250
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    • 2004
  • We have investigated the effects of boron added to Cu film on the Cu-Ti reaction and microstructural evolution of Cu(B) alloy film during annealing of Cu(B)/Ti/$SiO_2$/Si structure. The result were compared with those of Cu(B)/$SiO_2$ structure to identify the effects of Ti glue layers on the Boron behavior and the result grain growth of Cu(B) alloy. The vacuum annealing of Cu(B)/Ti/$SiO_2$ multilayer structure allowed the diffusion of B to the Ti surface and forming $TiB_2$ compounds at the interface. The formed $TiB_2$ can act as a excellent diffusion barrier against Cu-Ti interdiffusion up to $800^{\circ}C$. Also, the resistivity was decreased to $2.3\mu$$\Omega$-cm after annealing at $800^{\circ}C$. In addition, the presence of Ti underlayer promoted the growth Cu(l11)-oriented grains and allowed for normal growth of Cu(B) film. This is in contrast with abnormal growth of randomly oriented Cu grains occurring in Cu(B)/$SiO_2$ upon annealing. The Cu(B)/Ti/$SiO_2$ structure can be implemented as an advanced metallization because it exhibits the low resistivity, high thermal stability and excellent diffusion barrier property.

플립칩용 Sn-Cu 전해도금 솔더 범프의 형성 연구 (Formation of Sn-Cu Solder Bump by Electroplating for Flip Chip)

  • 정석원;강경인;정재필;주운홍
    • 마이크로전자및패키징학회지
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    • 제10권4호
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    • pp.39-46
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    • 2003
  • 플립칩용으로 Sn-Cu 공정 솔더 범프를 전해도금을 이용하여 제조하고 특성을 연구하였다. Si 웨이퍼 위에 UBM(Under Bump Metallization)으로 Al(400 nm)/Cu(300 nm)/Ni(400 nm)/Au(20 nm)를 전자빔 증착기로 증착하였다. 전류밀도가 1 A/d$\m^2$에서 8 A/d$\m^2$으로 증가함에 따라 Sn-Cu 솔더의 도금속도는 0.25 $\mu\textrm{m}$/min에서 2.7 $\mu\textrm{m}$/min으로 증가하였다. 이 전류밀도의 범위에서 전해도금된 Sn-Cu 도금 합금의 조성은 Sn-0.9∼1.4 wt%Cu의 거의 일정한 상태를 유지하였다. 도금 전류밀도 5 A/d$\m^2$, 도금시간 2hrs, 온도 $20^{\circ}C$의 조건에서 도금하였을 때, 기둥 직경 약 120 $\mu\textrm{m}$인 양호한 버섯 형태의 Sn-Cu 범프를 형성할 수 있었다. 버섯형 도금 범프를 $260^{\circ}C$에서 리플로우 했을 때 직경 약 140 $\mu\textrm{m}$의 구형 범프가 형성되었다. 화학성분의 균일성을 분석한 결과 버섯형 범프에서 존재하던 범프내 Sn 등 성분 원소의 불균일성은 구형 범프에서는 상당 부분 해소 되었다.

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