• Title/Summary/Keyword: crossbar array

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New Memristor-Based Crossbar Array Architecture with 50-% Area Reduction and 48-% Power Saving for Matrix-Vector Multiplication of Analog Neuromorphic Computing

  • Truong, Son Ngoc;Min, Kyeong-Sik
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.3
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    • pp.356-363
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    • 2014
  • In this paper, we propose a new memristor-based crossbar array architecture, where a single memristor array and constant-term circuit are used to represent both plus-polarity and minus-polarity matrices. This is different from the previous crossbar array architecture which has two memristor arrays to represent plus-polarity and minus-polarity connection matrices, respectively. The proposed crossbar architecture is tested and verified to have the same performance with the previous crossbar architecture for applications of character recognition. For areal density, however, the proposed crossbar architecture is twice better than the previous architecture, because only single memristor array is used instead of two crossbar arrays. Moreover, the power consumption of the proposed architecture can be smaller by 48% than the previous one because the number of memristors in the proposed crossbar architecture is reduced to half compared to the previous crossbar architecture. From the high areal density and high energy efficiency, we can know that this newly proposed crossbar array architecture is very suitable to various applications of analog neuromorphic computing that demand high areal density and low energy consumption.

Mixed-mode SNN crossbar array with embedded dummy switch and mid-node pre-charge scheme

  • Kwang-Il Oh;Hyuk Kim;Taewook Kang;Sung-Eun Kim;Jae-Jin Lee;Byung-Do Yang
    • ETRI Journal
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    • v.46 no.5
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    • pp.865-877
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    • 2024
  • This paper presents a membrane computation error-minimized mixed-mode spiking neural network (SNN) crossbar array. Our approach involves implementing an embedded dummy switch scheme and a mid-node pre-charge scheme to construct a high-precision current-mode synapse. We effectively suppressed charge sharing between membrane capacitors and the parasitic capacitance of synapses that results in membrane computation error. A 400 × 20 SNN crossbar prototype chip is fabricated via a 28-nm FDSOI CMOS process, and 20 MNIST patterns with their sizes reduced to 20 × 20 pixels are successfully recognized under 411 ㎼ of power consumed. Moreover, the peak-to-peak deviation of the normalized output spike count measured from the 21 fabricated SNN prototype chips is within 16.5% from the ideal value, including sample-wise random variations.

Electrical Conduction Mechanism in the Insulating TaNx Film (절연성 TaNx 박막의 전기전도 기구)

  • Ryu, Sungyeon;Choi, Byung Joon
    • Korean Journal of Materials Research
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    • v.27 no.1
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    • pp.32-38
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    • 2017
  • Insulating $TaN_x$ films were grown by plasma enhanced atomic layer deposition using butylimido tris dimethylamido tantalum and $N_2+H_2$ mixed gas as metalorganic source and reactance gas, respectively. Crossbar devices having a $Pt/TaN_x/Pt$ stack were fabricated and their electrical properties were examined. The crossbar devices exhibited temperature-dependent nonlinear I (current) - V (voltage) characteristics in the temperature range of 90-300 K. Various electrical conduction mechanisms were adopted to understand the governing electrical conduction mechanism in the device. Among them, the PooleFrenkel emission model, which uses a bulk-limited conduction mechanism, may successfully fit with the I - V characteristics of the devices with 5- and 18-nm-thick $TaN_x$ films. Values of ~0.4 eV of trap energy and ~20 of dielectric constant were extracted from the fitting. These results can be well explained by the amorphous micro-structure and point defects, such as oxygen substitution ($O_N$) and interstitial nitrogen ($N_i$) in the $TaN_x$ films, which were revealed by transmission electron microscopy and UV-Visible spectroscopy. The nonlinear conduction characteristics of $TaN_x$ film can make this film useful as a selector device for a crossbar array of a resistive switching random access memory or a synaptic device.

Implementation of real-time free-space optical interconnection using spatial light modulator (공간광변조기를 이용한 실시간 자유공간 광연결 구현)

  • Lee, Deug-Ju;Kang, Bong-Gyun;Kim, Nam;Suh, Ho-Hyung
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.22 no.5
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    • pp.956-966
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    • 1997
  • Dynamic free-space optical interconnection system is experimented by a holographic crossbar with single-state switching architecture. For dynamic operation, electrically addressed liquid-crystal spatial light modulator and diffraction gratings are used in place of passive holograms of matrix-matrix crossbar. Diffraction gratings are consisted of regular cells which have different phase delays. This pixelated phase grating array displayed on SLM(Spatial Light modulator) deflects an input beam toward a wanted direction or splits an input beam into many beams and then steers them to desired positions. Through the experimental results, free-space optical interconnection is dynamically perfomed using a computer, SLM and phase diffraction gratings.

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Si3N4/AlN 이중층 구조 소자의 자가 정류 특성

  • Gwon, Jeong-Yong;Kim, Hui-Dong;Yun, Min-Ju;Kim, Tae-Geun
    • Proceedings of the Korean Vacuum Society Conference
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    • 2014.02a
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    • pp.306.2-306.2
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    • 2014
  • 전자기기의 휴대성과 이동성이 강조되고 있는 현대사회에서 비휘발성 메모리는 메모리 산업에 있어 매우 매력적인 동시에 커다란 잠재성을 지닌다. 이미 공정의 한계에 부딪힌 Flash 메모리를 대신하여 10nm 이하의 공정이 가능한 상변화 메모리(Phase-Change Memory, PRAM), 스핀 주입 자화 반전 메모리(Spin Transfer Torque-Magnetic RAM, STT-MRAM), 저항 변화 메모리(Resistive Random Access Memory, ReRAM)가 차세대 비휘발성 메모리 후보로서 거론되고 있으며, 그 중에서도 ReRAM은 빠른 속도와 낮은 소비 전력, CMOS 공정 호환성, 그리고 비교적 단순한 3차원 적층 구조의 특성으로 인해 활발히 연구되고 있다. 특히 최근에는 질화물 또는 질소를 도핑한 산화물을 저항변화 물질로 사용하는 ReRAM이 보고되고 있는데, 이들은 동작전압이 낮을 뿐만 아니라 저항 변화(Resistive Switching, RS) 과정에서 일어나는 계면 산화를 방지할 수 있으므로 ReRAM의 저항 변화 재료로서 각광받고 있다. 그러나 Cell 단위의 ReRAM 소자를 Crossbar Array 구조에 적용시켰을 때 주변 Cell과의 저항 상태 차이로 인해 전류가 낮은 저항 상태(LRS)의 Cell로 흘러 의도치 않은 동작을 야기한다. 이와 같이 누설 전류(Leakage Current)로 인한 상호간의 간섭이 일어나는 Cross-talk 현상이 존재하며, 공정의 간소화와 집적도를 유지하면서 이 문제를 해결하는 것은 실용화하기에 앞서 매우 중요한 문제이다. 따라서, 본 논문에서는 Read 동작 시 발생하는 Cell과 Cell 사이의 Cross-talk 문제를 해결하기 위해 자가 정류 특성(Self-Rectifying)을 가지는 실리콘 질화물/알루미늄 질화물 이중층(Si3N4/AlN Bi-layer)으로 구성된 ReRAM 소자 구조를 제안하였으며, Sputtering 방법을 이용하여 제안된 소자를 제작하였다. 전압-전류 특성 실험결과, 제안된 구조에 대한 에너지 밴드 다이어그램 시뮬레이션 결과와 동일하게 Positive Bias 영역에서 자가 정류 특성을 획득하였고, 결과적으로 Read 동작 시 발생하는 Cross-talk 현상을 차단할 수 있는 결과를 확보하였다.

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The Latest Trends and Issues of Anion-based Memristor (음이온 기반 멤리스터의 최신 기술동향 및 이슈)

  • Lee, Hong-Sub
    • Journal of the Microelectronics and Packaging Society
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    • v.26 no.1
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    • pp.1-7
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    • 2019
  • Recently, memristor (anion-based memristor) is referred to as the fourth circuit element which resistance state can be gradually changed by the electric pulse signals that have been applied to it. And the stored information in a memristor is non-volatile and also the resistance of a memristor can vary, through intermediate states, between high and low resistance states, by tuning the voltage and current. Therefore the memristor can be applied for analogue memory and/or learning device. Usually, memristive behavior is easily observed in the most transition metal oxide system, and it is explained by electrochemical migration motion of anion with electric field, electron scattering and joule heating. This paper reports the latest trends and issues of anion-based memristor.

Fabric Mapping and Placement of Field Programmable Stateful Logic Array (Field Programmable Stateful Logic Array 패브릭 매핑 및 배치)

  • Kim, Kyosun
    • Journal of the Institute of Electronics and Information Engineers
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    • v.49 no.12
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    • pp.209-218
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    • 2012
  • Recently, the Field Programmable Stateful Logic Array (FPSLA) was proposed as one of the most promising system integration technologies which will extend the life of the Moore's law. This work is the first proposal of the FPSLA design automation flow, and the approaches to logic synthesis, synchronization, physical mapping, and automatic placement of the FPSLA designs. The synchronization at each gate for pipelining determines the x-coordinates of cells, and reduces the placement to 1-dimensional problems. The objective function and its gradients for the non-linear optimization of the net length and placement density have been remodeled for the reduced global placement problem. Also, a recursive algorithm has been proposed to legalize the placement by relaxing the density overflow of bipartite bin groups in a top-down hierarchical fashion. The proposed model and algorithm are implemented, and validated by applying them to the ACM/SIGDA benchmark designs. The output state of a gate in an FPSLA needs to be duplicated so that each fanout gate can be connected to a dedicated copy. This property has been taken into account by merging the duplicated nets into a hyperedge, and then, splitting the hyperedge into edges as the optimization progresses. This yields additional 18.4% of the cell count reduction in the most dense logic stage. The practicality of the FPSLA can be further enhanced primarily by incorporating into the logic synthesis the constraint to avoid the concentrated fains of gates on some logic stages. In addition, an efficient algorithm needs to be devised for the routing problem which is based on a complicated graph. The graph models the nanowire crossbar which is trimmed to be embedded into the FPSLA fabric, and therefore, asymmetric. These CAD tools can be used to evaluate the fabric efficiency during the architecture enhancement as well as automate the design.

Current Versus Voltage Characteristics of a Si Based 1-Diode Type Resistive Memory with Cr-SrTiO3 Films (Cr-SrTiO3 박막을 이용한 Si 기반 1D 형태 저항 변화 메모리의 전류-전압 특성 고찰)

  • Song, Min-Yeong;Seo, Yu-Jeong;Kim, Yeon-Soo;Kim, Hee-Dong;An, Ho-Myoung;Kim, Tae-Geun
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.24 no.11
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    • pp.855-858
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    • 2011
  • In this paper, in order to suppress unwanted current paths originating from adjacent cells in a passive crossbar array based on resistive random access memory (RRAM) without extrinsic switching devices, 1-diode type RRAM which consists of a 0.2% chromium-doped strontium titanate (Cr-$SrTiO_3$) film deposited on a silicon substrate, was proposed for high packing density, and intrinsic rectifying characteristics from the current versus voltage characteristics were successfully demonstrated.

1 Selector + 1 Resistance Behavior Observed in Pt/SiN/Ti/Si Structure Resistive Switching Memory Cells

  • Park, Ju-Hyeon;Kim, Hui-Dong;Kim, Tae-Geun
    • Proceedings of the Korean Vacuum Society Conference
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    • 2014.02a
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    • pp.307-307
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    • 2014
  • 정보화 시대로 접어들면서 동일한 공간에 더 많은 정보를 저장할 수 있고, 보다 빠른 동작이 가능한 비휘발성 메모리 소자에 대한 요구가 증가하고 있다. 하지만, 최근 비휘발성 메모리 소자 관련 연구보고에 따르면, 메모리 소자의 소형화 및 직접화 측면에서, 전하 저장을 기반으로 하는 기존의 Floating-Gate(FG) Flash 메모리는 20 nm 이하 공정에서 한계가 예측 되고 있다. 따라서, 이러한 FG Flash 메모리의 한계를 해결하기 위해, 기존에 FET 기반의 FG Flash 구조와 같은 3 terminal이 아닌, Diode와 같은 2 terminal로 동작이 가능한 ReRAM, PRAM, STT-MRAM, PoRAM 등 저항변화를 기반으로 하는 다양한 종류의 차세대 메모리 소자가 연구되고 있다. 그 중, 저항 변화 메모리(ReRAM)는 CMOS 공정 호환성, 3D 직접도, 낮은 소비전력과 빠른 동작 속도 등의 우수한 동작 특성을 가져 차세대 비휘발성 메모리로 주목을 받고 있다. 또한, 상하부 전극의 2 terminal 만으로 소자 구동이 가능하기 때문에 Passive Crossbar-Array(CBA)로 적용하여 플래시 메모리를 대체할 수 있는 유력한 차세대 메모리 소자이다. 하지만, 이를 현실화하기 위해서는 Passive CBA 구조에서 발생할 수 있는 Read Disturb 현상, 즉 Word-Line과 Bit-Line을 통해 선택된 소자를 제외하고 주변의 다른 소자를 통해 흐르는 Sneak Leakage Current(SLC)를 차단하여 소자의 메모리 State를 정확히 sensing하기 위한 연구가 선행 되어야 한다. 따라서, 현재 이러한 이슈를 해결하기 위해서, 많은 연구 그룹에서 Diodes, Threshold Switches와 같은 ReRAM에 Selector 소자를 추가하는 방법, 또는 Self-Rectifying 특성 및 CRS 특성을 보이는 ReRAM 구조를 제안 하여 SLC를 차단하고자 하는 연구가 시도 되고 있지만, 아직까지 기초연구 단계로서 아이디어에 대한 가능성 정도만 보고되고 있는 현실 이다. 이에 본 논문은 Passive CBA구조에서 발생하는 SLC를 해결하기 위한 새로운 아이디어로써, 본 연구 그룹에서 선행 연구로 확보된 안정적인 저항변화 물질인 SiN를 정류 특성을 가지는 n-Si/Ti 기반의 Schottky Diode와 결합함으로써 기존의 CBA 메모리의 Read 동작에서 발생하는 SLC를 차단 할 수 있는 1SD-1R 구조의 메모리 구조를 제작 하였으며, 본 연구 결과 기존에 문제가 되었던 SLC를 차단 할 수 있었다.

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Resistive Switching Characteristic of Direct-patternable Amorphous TiOx Film by Photochemical Metal-organic Deposition (광화학증착법에 의한 직접패턴 비정질 TiOx 박막의 제조 및 저항변화 특성)

  • Hwang, Yun-Kyeong;Lee, Woo-Young;Lee, Se-Jin;Lee, Hong-Sub
    • Journal of the Microelectronics and Packaging Society
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    • v.27 no.1
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    • pp.25-29
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    • 2020
  • This study demonstrates direct-patternable amorphous TiOx resistive switching (RS) device and the fabrication method using photochemical metal-organic deposition (PMOD). For making photosensitive stock solutions, Ti(IV) 2-ethylhexanoate was used as starting precursor. Photochemical reaction by UV exposure was observed and analyzed by Fourier transform infrared spectroscopy and the reaction was completed within 10 minutes. Uniformly formed 20 nm thick amorphous TiOx film was confirmed by atomic force microscopy. Amorphous TiOx RS device, formed as 6 × 6 ㎛ square on 4 ㎛ width electrode, showed forming-less RS behavior in ±4 V and on/off ratio ≈ 20 at 0.1 V. This result shows PMOD process could be applied for low temperature processed ReRAM device and/or low cost, flexible memory device.