• JSTS:Journal of Semiconductor Technology and Science
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• 제14권3호
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• pp.356-363
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• 2014

In this paper, we propose a new memristor-based crossbar array architecture, where a single memristor array and constant-term circuit are used to represent both plus-polarity and minus-polarity matrices. This is different from the previous crossbar array architecture which has two memristor arrays to represent plus-polarity and minus-polarity connection matrices, respectively. The proposed crossbar architecture is tested and verified to have the same performance with the previous crossbar architecture for applications of character recognition. For areal density, however, the proposed crossbar architecture is twice better than the previous architecture, because only single memristor array is used instead of two crossbar arrays. Moreover, the power consumption of the proposed architecture can be smaller by 48% than the previous one because the number of memristors in the proposed crossbar architecture is reduced to half compared to the previous crossbar architecture. From the high areal density and high energy efficiency, we can know that this newly proposed crossbar array architecture is very suitable to various applications of analog neuromorphic computing that demand high areal density and low energy consumption.

• 한국정보과학회논문지:시스템및이론
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• 제37권5호
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• pp.257-271
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• 2010

Photolithography 통합 시대의 끝이 빠르게 다가옴에 따라, 최근에는 새로운 나노 스케일의 소재와 집적 방식에 기반을 둔 수많은 나노 스케일 장치와 시스템이 나타나고 있다. 특히 nanowire crossbar 구조를 이용한 다양한 reconfigurable architecture 들이 보고되고 있다. 하지만 아쉽게도 나노 스케일의 구성 요소를 이용한 이러한 고집적 시스템은 생산 단계에서 발생하는 각종 물리적 결함과 오차에 취약하며 따라서 결함에 대한 관용성 즉 defecttolerance는 nanowire reconfigurable crossbar 시스템에 있어 해결해야 할 가장 중대한 문제 중 하나라 할 수 있다. 이에 본 논문에서는 nanowire reconfigurable crossbar 시스템 상에서 사용되어질 수 있는 세 가지의 결함 회피형(defectavoidant) 로직 재할당 알고리듬을 설명하고 다양한 방식으로 평가하였다. 이에 더불어 로직 재할당시에 발생하는 비용과 이로 인해 얻어지는 repair performance를 계량적으로 상호 분석하여 최적화된 repair 방식을 찾아내는 새로운 방안을 소개하였다. 이어 다양한 파라메터들을 이용한 시뮬레이션 결과를 제시함으로써 새로 소개된 cost-driven repair 최적화 방식을 검증하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권1호
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• pp.77-84
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• 2015

This paper presents the design of a low-power, low area 256-radix 16-bit crossbar switch employing a 2D Hyper-X network topology. The Hyper-X crossbar switch realizes the high radix of 256 by hierarchically combining a set of 4-radix sub-switches and applies three modifications to the basic Hyper-X topology in order to mitigate the adverse scaling of power consumption and propagation delay with the increasing radix. For instance, by restricting the directions in which signals can be routed, by restricting the ports to which signals can be connected, and by replacing the column-wise routes with diagonal routes, the fanout of each circuit node can be substantially reduced from 256 to 4~8. The proposed 256-radix, 16-bit crossbar switch is designed in a 65 nm CMOS and occupies the total area of $0.93{\times}1.25mm^2$. The simulated worst-case delay and power dissipation are 641 ps and 13.01 W when operating at a 1.2 V supply and 1 GHz frequency. In comparison with the state-of-the-art designs, the proposed crossbar switch design achieves the best energy-delay efficiency of $2.203cycle/ns{\cdot}fJ{\cdot}{\lambda}2$.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권6호
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• pp.760-767
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• 2014

This paper describes a high-radix crossbar switch design with low latency and power dissipation for Network-on-Chip (NoC) applications. The reduction in latency and power is achieved by employing a folded-clos topology, implementing the switch organized as three stages of low-radix switches connected in cascade. In addition, to facilitate the uniform placement of wires among the sub-switch stages, this paper proposes a Mux-Matrix-Mux structure, which implements the first and third switch stages as multiplexer-based crossbars and the second stage as a matrix-type crossbar. The proposed 256-radix, 8-bit crossbar switch designed in a 65nm CMOS has the simulated power dissipation of 1.92-W and worst-case propagation delay of 0.991-ns while operating at 1.2-V supply and 500-MHz frequency. Compared with the state-of-the-art designs in literature, the proposed crossbar switch achieves the best energy-delay-area efficiency of $0.73-fJ/cycle{\cdot}ns{\cdot}{\lambda}^2$.

• 한국군사과학기술학회지
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• 제4권2호
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• pp.122-129
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• 2001

A characterization procedure for analyzing symmetric coupled MIS(Metal-Insulator-Semiconductor) transmission line is used the same procedure as a general single layer symmetric coupled line with perfect dielectric substrate from the extraction of the characteristic impedance and propagation constant for even- and odd-mode. In this paper, an analysis for a new substrate shielding symmetric coupled MIS structure consisting of grounded crossbar at the interface between Si and SiO2 layer using the Finite- Difference Time-Domain(FDTD) method is presented. In order to reduce the substrate effects on the transmission line characteristics, a shielding structure consisting of grounded crossbar lines over time-domain signal has been examined. Symmetric coupled MIS transmission line parameters for even- and odd-mode are investigated as the functions of frequency, and the extracted distributed frequency- dependent transmission line parameters and corresponding equivalent circuit parameters as well as quality factor for the new MIS crossbar embedded structure are also presented. It is shown that the quality factor of the symmetric coupled transmission line can be improved without significant change in the characteristic impedance and effective dielectric constant.

• ETRI Journal
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• 제26권5호
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• pp.505-508
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• 2004

We propose a new arbitration method for an input buffered switch with a buffered crossbar. In the proposed method, an exhaustive polling method is used to decrease the synchronization. Using an approximate analysis, we explain how the proposed method improves the switch performance. Also, using computer simulations, we show the proposed method outperforms the previous methods under burst traffic.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권4호
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• pp.318-328
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• 2011

Stage-level reconfigurable chip multiprocessor (CMP) aims to achieve highly reliable and fault tolerant computing by using interwoven pipeline stages and on-chip interconnect for communicating with each other. The existing crossbar-switch based stage-level reconfigurable CMPs offer high reliability at the cost of significant area/power overheads. These overheads make realizing large CMPs prohibitive due to the area and power consumed by heavy interconnection networks. On other hand, area/power-efficient architectures offer less reliability and inefficient stage-level resource utilization. In this paper, I propose a hierarchical multiplexing interconnection structure in lieu of crossbar interconnect to design area/power-efficient stage-level reconfigurable CMP. The proposed approach is able to keep the reliability offered by the crossbar-switch while reducing the area and power overheads. Experimental results show that the proposed approach reduces area by up to 21% and power by up to 32% when compared with the crossbar-switch based interconnection network.

• 한국초전도저온공학회:학술대회논문집
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• 한국초전도저온공학회 2003년도 추계학술대회 논문집
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• pp.146-149
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• 2003

In this Work, we have studied about an RSFQ 2$\times$2 crossbar switch. The circuit was designed, simulated, and laid out for mask fabrication The switch cell was composed of a splitter a confluence buffer, and a switch core. An RSFQ 2$\times$2 crossbar switch was composed of 4 switch cells, a switch control input to select the cross and bar, data input, and data outputs. When a pulse was input to the switch control input to select the cross or bar the route of the input data was determined, and the data was output at the proper output port. We simulated and optimized the switch-element circuit and 2$\times$2 crossbar switch, by using Xic and Julia. We also performed the mask layout of the circuit by using Xic and Lmeter.

• Clinics in Shoulder and Elbow
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• 제22권3호
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• pp.149-153
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• 2019

We experienced acromial erosion and subsequent fracture after the treatment of Rockwood type V acromioclavicular dislocation with hook plate and coracoclavicular ligament augmentation. It was treated by using a surgical technique to address an acromial fracture and subsequent losses of reduction in acromioclavicular joint with two trans-acromial cortical screws (crossbar technique). The reduction state of acromioclavicular joint could be maintained by these two screws. Our crossbar technique could be considered as a good salvage procedure for the reduction loss caused by cutout or significant erosion of acromion after insertion of clavicular hook plate.

• 전자공학회논문지
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• 제50권1호
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• pp.166-173
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• 2013

SoC내의 IP 개수 및 데이터 통신량이 증가함에 따라 온칩 크로스바 네트워크가 SoC의 중추 연결망으로서 널리 사용되어지고 있다. 온칩 크로스바 네트워크는 여러 개의 크로스바 스위치들과 이들간의 연결로 이루어지는데, 시스템의 복잡도가 증가함에 따라 IP들과 스위치들간의 연결 형태를 결정하는 것, 즉 토폴로지를 결정하는 것이 점점 복잡해지고 있다. 이 문제를 해결하기 위해 본 논문에서는 목표 시스템의 칩내 통신 특성을 고려하여 최적의 온칩 크로스바 네트워크의 토폴로지를 찾아주는 방법을 제안한다. 제안하는 토폴로지 합성 방법은 mixed integer linear programming(MIILP)를 이용하여 다른 휴리스틱 합성 방법과 달리 전역 최적점(global optimum)을 찾을 수 있는 장점이 있다. 또한, 기존에 제안 되었던 MILP를 이용한 토폴로지 합성 방법들이 토폴로지를 표현하는데 IP 노드들과 스위치들 간의 인접 행렬들을 이용했던 것과 달리, 본 논문에서는 IP들 간통신을 표현하는 엣지들을 기본으로 하는 새로운 표현 방식을 제안한다. 실험 결과 본 논문에서 제안하는 새로운 MILP 표현 방식을 이용할 경우 기존 MILP 표현 방식을 이용했을 때보다 4개의 예제들에 대해 합성 속도가 평균 77.1 배 향상되었다.