• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.356-363
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• 2014

In this paper, we propose a new memristor-based crossbar array architecture, where a single memristor array and constant-term circuit are used to represent both plus-polarity and minus-polarity matrices. This is different from the previous crossbar array architecture which has two memristor arrays to represent plus-polarity and minus-polarity connection matrices, respectively. The proposed crossbar architecture is tested and verified to have the same performance with the previous crossbar architecture for applications of character recognition. For areal density, however, the proposed crossbar architecture is twice better than the previous architecture, because only single memristor array is used instead of two crossbar arrays. Moreover, the power consumption of the proposed architecture can be smaller by 48% than the previous one because the number of memristors in the proposed crossbar architecture is reduced to half compared to the previous crossbar architecture. From the high areal density and high energy efficiency, we can know that this newly proposed crossbar array architecture is very suitable to various applications of analog neuromorphic computing that demand high areal density and low energy consumption.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.5
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• pp.257-271
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• 2010

As the end of photolithographic integration era is approaching fast, numerous nanoscale devices and systems based on novel nanoscale materials and assembly techniques are recently emerging. Notably, various reconfigurable architectures with considerable promise have been proposed based on nanowire crossbar structure as the primitive building block. Unfortunately, high-density sys-tems consisting of nanometer-scale elements are likely to have numerous physical imperfections and variations. Therefore, defect-tolerance is considered as one of the most exigent challenges in nanowire crossbar systems. In this work, three different defect-avoidant logic mapping algorithms to circumvent defective crosspoints in nanowire reconfigurable crossbar systems are evaluated in terms of various performance metrics. Then, a novel method to find the most cost-effective repair solution is demonstrated by considering all major repair parameters and quantitatively estimating the performance and cost-effectiveness of each algorithm. Extensive parametric simulation results are reported to compare overall repair costs of the repair algorithms under consideration and to validate the cost-driven repair optimization technique.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.77-84
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• 2015

This paper presents the design of a low-power, low area 256-radix 16-bit crossbar switch employing a 2D Hyper-X network topology. The Hyper-X crossbar switch realizes the high radix of 256 by hierarchically combining a set of 4-radix sub-switches and applies three modifications to the basic Hyper-X topology in order to mitigate the adverse scaling of power consumption and propagation delay with the increasing radix. For instance, by restricting the directions in which signals can be routed, by restricting the ports to which signals can be connected, and by replacing the column-wise routes with diagonal routes, the fanout of each circuit node can be substantially reduced from 256 to 4~8. The proposed 256-radix, 16-bit crossbar switch is designed in a 65 nm CMOS and occupies the total area of $0.93{\times}1.25mm^2$. The simulated worst-case delay and power dissipation are 641 ps and 13.01 W when operating at a 1.2 V supply and 1 GHz frequency. In comparison with the state-of-the-art designs, the proposed crossbar switch design achieves the best energy-delay efficiency of $2.203cycle/ns{\cdot}fJ{\cdot}{\lambda}2$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.760-767
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• 2014

This paper describes a high-radix crossbar switch design with low latency and power dissipation for Network-on-Chip (NoC) applications. The reduction in latency and power is achieved by employing a folded-clos topology, implementing the switch organized as three stages of low-radix switches connected in cascade. In addition, to facilitate the uniform placement of wires among the sub-switch stages, this paper proposes a Mux-Matrix-Mux structure, which implements the first and third switch stages as multiplexer-based crossbars and the second stage as a matrix-type crossbar. The proposed 256-radix, 8-bit crossbar switch designed in a 65nm CMOS has the simulated power dissipation of 1.92-W and worst-case propagation delay of 0.991-ns while operating at 1.2-V supply and 500-MHz frequency. Compared with the state-of-the-art designs in literature, the proposed crossbar switch achieves the best energy-delay-area efficiency of $0.73-fJ/cycle{\cdot}ns{\cdot}{\lambda}^2$.

• Journal of the Korea Institute of Military Science and Technology
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• v.4 no.2
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• pp.122-129
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• 2001

A characterization procedure for analyzing symmetric coupled MIS(Metal-Insulator-Semiconductor) transmission line is used the same procedure as a general single layer symmetric coupled line with perfect dielectric substrate from the extraction of the characteristic impedance and propagation constant for even- and odd-mode. In this paper, an analysis for a new substrate shielding symmetric coupled MIS structure consisting of grounded crossbar at the interface between Si and SiO2 layer using the Finite- Difference Time-Domain(FDTD) method is presented. In order to reduce the substrate effects on the transmission line characteristics, a shielding structure consisting of grounded crossbar lines over time-domain signal has been examined. Symmetric coupled MIS transmission line parameters for even- and odd-mode are investigated as the functions of frequency, and the extracted distributed frequency- dependent transmission line parameters and corresponding equivalent circuit parameters as well as quality factor for the new MIS crossbar embedded structure are also presented. It is shown that the quality factor of the symmetric coupled transmission line can be improved without significant change in the characteristic impedance and effective dielectric constant.

• ETRI Journal
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• v.26 no.5
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• pp.505-508
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• 2004

We propose a new arbitration method for an input buffered switch with a buffered crossbar. In the proposed method, an exhaustive polling method is used to decrease the synchronization. Using an approximate analysis, we explain how the proposed method improves the switch performance. Also, using computer simulations, we show the proposed method outperforms the previous methods under burst traffic.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.318-328
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• 2011

Stage-level reconfigurable chip multiprocessor (CMP) aims to achieve highly reliable and fault tolerant computing by using interwoven pipeline stages and on-chip interconnect for communicating with each other. The existing crossbar-switch based stage-level reconfigurable CMPs offer high reliability at the cost of significant area/power overheads. These overheads make realizing large CMPs prohibitive due to the area and power consumed by heavy interconnection networks. On other hand, area/power-efficient architectures offer less reliability and inefficient stage-level resource utilization. In this paper, I propose a hierarchical multiplexing interconnection structure in lieu of crossbar interconnect to design area/power-efficient stage-level reconfigurable CMP. The proposed approach is able to keep the reliability offered by the crossbar-switch while reducing the area and power overheads. Experimental results show that the proposed approach reduces area by up to 21% and power by up to 32% when compared with the crossbar-switch based interconnection network.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2003.10a
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• pp.146-149
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• 2003

In this Work, we have studied about an RSFQ 2$\times$2 crossbar switch. The circuit was designed, simulated, and laid out for mask fabrication The switch cell was composed of a splitter a confluence buffer, and a switch core. An RSFQ 2$\times$2 crossbar switch was composed of 4 switch cells, a switch control input to select the cross and bar, data input, and data outputs. When a pulse was input to the switch control input to select the cross or bar the route of the input data was determined, and the data was output at the proper output port. We simulated and optimized the switch-element circuit and 2$\times$2 crossbar switch, by using Xic and Julia. We also performed the mask layout of the circuit by using Xic and Lmeter.

• Clinics in Shoulder and Elbow
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• v.22 no.3
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• pp.149-153
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• 2019

We experienced acromial erosion and subsequent fracture after the treatment of Rockwood type V acromioclavicular dislocation with hook plate and coracoclavicular ligament augmentation. It was treated by using a surgical technique to address an acromial fracture and subsequent losses of reduction in acromioclavicular joint with two trans-acromial cortical screws (crossbar technique). The reduction state of acromioclavicular joint could be maintained by these two screws. Our crossbar technique could be considered as a good salvage procedure for the reduction loss caused by cutout or significant erosion of acromion after insertion of clavicular hook plate.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.166-173
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• 2013

As the number of IPs and the communication volume among them have constantly increased, on-chip crossbar network is now the most widely-used on-chip communication backbone of contemporary SoCs. The on-chip crossbar network consists of multiple crossbars and the connections among the IPs and the crossbars. As the complexity of SoCs increases, it has also become more and more complex to determine the topology of the crossbar network. To tackle this problem, this paper proposes an on-chip crossbar network topology method for application-specific systems. The proposed method uses mixed integer linear programming to solve the topology synthesis problem, thus the global optimality is guaranteed. Unlike the previous MILP-based methods which represent the topology with adjacency matrixes of IPs and crossbar switches, the proposed method uses the communication edges among IPs as the basic element of the representation. The experimental results show that the proposed MILP formulation outperforms the previous one by improving the synthesis speed by 77.1 times on average, for 4 realistic benchmarks.