• Title/Summary/Keyword: critical decimation

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Analysis of decimation techniques to improve computational efficiency of a frequency-domain evaluation approach for real-time hybrid simulation

  • Guo, Tong;Xu, Weijie;Chen, Cheng
    • Smart Structures and Systems
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    • v.14 no.6
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    • pp.1197-1220
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    • 2014
  • Accurate actuator tracking is critical to achieve reliable real-time hybrid simulation results for earthquake engineering research. The frequency-domain evaluation approach provides an innovative way for more quantitative post-simulation evaluation of actuator tracking errors compared with existing time domain based techniques. Utilizing the Fast Fourier Transform the approach analyzes the actuator error in terms of amplitude and phrase errors. Existing application of the approach requires using the complete length of the experimental data. To improve the computational efficiency, two techniques including data decimation and frequency decimation are analyzed to reduce the amount of data involved in the frequency-domain evaluation. The presented study aims to enhance the computational efficiency of the approach in order to utilize it for future on-line actuator tracking evaluation. Both computational simulation and laboratory experimental results are analyzed and recommendations on the two decimation factors are provided based on the findings from this study.

Affine Projection Algorithm for Subband Adaptive Filters with Critical Decimation and Its Simple Implementation (임계 데시메이션을 갖는 부밴드 적응필터를 위한 인접 투사 알고리즘과 간단한 구현)

  • Choi, Hun;Bae, Hyeon-Deok
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.42 no.5 s.305
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    • pp.145-156
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    • 2005
  • In application for acoustic echo cancellation and adaptive equalization, input signal is highly correlated and the long length of adaptive filter is needed. Affine projection algorithms, in these applications, can produce a good convergence performance. However, they have a drawback that is a complex hardware implementation. In this paper, we propose a new subband affine projection algorithm with improved convergence and reduced computational complexity. In addition, we suggest a good approach to implement the proposed method. In this method by applying polyphase decomposition, noble identity and critical decimation to the anne projection algorithm the number of input vectors for decorrelation can be reduced. The weight-updating formula of the proposed method is derived as a simple form that compared with the NLMS(normalized least mean square) algorithm by the reduced projection order The efficiency of the proposed algorithm for a colored input signal was evaluated by using computer simulations.

Wavelet-Based Level-of-Detail Representation of 3D Objects (웨이브릿 기반의 3차원 물체 LOD 표현)

  • Lee, Ha-Sup;Yang, Hyun-Seung
    • Journal of KIISE:Computer Systems and Theory
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    • v.29 no.4
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    • pp.185-191
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    • 2002
  • In this paper, we propose a 3D object LOD(Level of Detail) modeling system that constructs a mesh from range images and generates the mesh of various LOD using the wavelet transform. In the initial mesh generation, we use the marching cube algorithm. We modify the original algorithm to apply it to construct the mesh from multiple range images efficiently. To get the base mesh we use the decimation algorithm which simplifies a mesh with preserving the topology Finally, when reconstructing new mesh which is similar to initial mesh we calculate the wavelet coefficients by using the wavelet transform. We solve the critical problem of wavelet-based methods - the surface crease problem (1) - by using the mesh simplification as the base mesh generation method.

Design of A High Performance 1-D Discrete Wavelet Transform Filter Using Pipelined Architecture (파이프라인 구조를 이용한 고성능 1 차원 이산 웨이블렛 변환 필터 설계)

  • Park, Tae-Geun;Song, Chang-Joo
    • Proceedings of the Korea Information Processing Society Conference
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    • 2001.10a
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    • pp.711-714
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    • 2001
  • 본 논문에서는 파이프라인 구조를 이용하여 고성능 1 차원 이산 웨이블렛 변환 필터를 설계하였다. 각 레벨에서 입력이 다운샘플링(downsampling, decimation)되므로 각 레벨의 하드웨어를 폴딩(folding) 기법을 이용하여 곱셈기와 덧셈기를 공유함으로써 복잡도를 개선하였다. 즉, 제안한 구조에서는 레벨 2 와 레벨 3 에서 폴딩된 구조의 C.S.R(Circular Shift Register)곱셈기와 덧셈기를 사용함으로써 하드웨어 효율(hardware utilization)을 각 레벨에서 100%로 높일 수 있다. 또한, 홀수와 짝수의 샘플을 병렬로 입력함으로써 단일 입력의 시스템과 비교할 때, 동일 시간에 병렬화 만큼의 이득을 얻을 수 있었고, 필터 계수는 미러 필터(mirror filter)의 특성을 이용하여 쳐대한 고역 필터(high pass filter)와 저역 필터(low pass filter)의 계수들을 공유함으로써 곱셈기와 덧셈기의 수를 반으로 줄였다. 그리고 임계 경로(critical path)를 줄이기 위한 파이프라인 레지스터를 삽입하여 고성능 시스템을 구현하였다.

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