• Journal of IKEEE
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• v.17 no.2
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• pp.119-128
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• 2013

This paper proposes and implements an core transform architecture, which is one of the major processes in HEVC video compression standard. The proposed core transform architecture is implemented with only adders and shifters instead of area-consuming multipliers. Shifters in the proposed core transform architecture are implemented in wires and multiplexers, which significantly reduces chip area. Also, it can process from $4{\times}4$ to $16{\times}16$ blocks with common hardware by reusing processing elements. Designed core transform architecture in 0.13um technology can process a $16{\times}16$ block with 2-D transform in 130 cycles, and its gate count is 101,015 gates.

• Journal of IKEEE
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• v.19 no.3
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• pp.378-384
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• 2015

In conventional HEVC inverse core transform architectures, extra $n{\times}n$ inverse transform block is added to $2n{\times}2n$ inverse transform block, and it operates as one $2n{\times}2n$ inverse transform block or two $n{\times}n$ inverse transform blocks. Thus, same number of pixels are processed in the same time, but it suffers from increased hardware size due to extra $n{\times}n$ inverse transform block. To avoid this problem, a novel $8{\times}8$ HEVC inverse core transform architecture was proposed to eliminate extra $4{\times}4$ inverse transform block based on multiplier reuse. This paper extends this approach and proposes a novel HEVC $16{\times}16$ inverse core transform architecture. Its frame processing time is same in $4{\times}4$, $8{\times}8$, and $16{\times}16$ inverse core transforms, and reduces gate counts by 13%.

• Journal of IKEEE
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• v.17 no.4
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• pp.570-578
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• 2013

This paper proposed an $8{\times}8$ HEVC inverse core transform architecture reusing multipliers. In HEVC core transform, processing of lower size block is identical with even part of upper size block. So an $8{\times}8$ core transform architecture can process both $8{\times}8$ and $4{\times}4$ core transforms. However, when $8{\times}8$ core transform architecture is exploited, frame processing time doubles in $4{\times}4$ core transform, since $8{\times}8$ and $4{\times}4$ core transforms concurrently process 8 and 4 pixels, respectively. In this paper, a novel inverse core transform architecture is proposed based on multiplier reuse. It runs as an $8{\times}8$ inverse core transformer or two $4{\times}4$ inverse core transformer. Its frame processing time is same in $8{\times}8$ and $4{\times}4$ core transforms, and reduces gate counts by 12%.

• Journal of IKEEE
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• v.15 no.3
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• pp.255-260
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• 2011

In this paper, we propose a parallelization technique in lane detection by using Hough transform. Hough transform has a weakness that it has a lot computation quantity, because it has to compute ${\rho}$ value in all candidate ${\Theta}$ to be detected in an image. We propose an architecture of parallel processing for this transform in a multi-core environment. The parallel processing has application to Hough transform as well as noise reduction and edge detection. This proposed architecture has 5.17 times improvement in performance compare to the existing algorithm.

• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.5
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• pp.277-284
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• 2012

To meet the usage of discrete wavelet transform (DWT) on potable devices, this paper implements 2-level DWT using a reference many-core processor architecture and determine the optimal many-core processor. To explore the optimal many-core processor, we evaluate the impacts of a data-per-processing element ratio that is defined as the amount of data mapped directly to each processing element (PE) on system performance, energy efficiency, and area efficiency, respectively. This paper utilized five PE configurations (PEs=16, 64, 256, 1,024, and 4,096) that were implemented in 130nm CMOS technology with a 720MHz clock frequency. Experimental results indicated that maximum energy and area efficiencies were achieved at PEs=1,024. However, the system area must be limited 140mm2 and the power should not exceed 3 watts in order to implement 2-level DWT on portable devices. When we consider these restrictions, the most reasonable energy and area efficiencies were achieved at PEs=256.

• Nuclear Engineering and Technology
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• v.29 no.5
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• pp.399-405
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• 1997

In this study a new phase separated spectral analysis algorithm is proposed to identify CSB vibration mode directly from ex-core neutron signals. Ex-core neutron signals can be decomposed into the global, core support barrel (CSB) beam mode, and CSB shell mode components by the new phase separation algorithm based on the characteristics of Fourier transform. By using the proposed algorithm and the conventional spectral analysis the vibration mode of the CSB and the fuel assembly of Ulchin-1 NPP were identified from measured ex-core neutron signals.

• Smart Media Journal
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• v.1 no.2
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• pp.6-11
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• 2012

In the HEVC standard, transform coefficient coding that affects the output bitstream directly is a core part of the encoder and it includes coefficient scanning and entropy coding. Recently, JCT-VC(Joint Collaborative Team on Video Coding) advances to HEVC Committee Draft (CD). In this paper, we explain HEVC transform coefficient coding and propose an efficient transform coefficient coding method considering statistics of transform coefficients in the intra frame coder. The proposed method reduces BD-Rate by up to 0.74%, compared to the conventional HEVC transform coefficient coding.

• Journal of the Korea Society of Computer and Information
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• v.18 no.9
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• pp.1-10
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• 2013

In this paper, we implement the SIFT(Scale-Invariant Feature Transform) algorithm for feature point extraction using a many-core processor, and analyze the performance, area efficiency, and system area efficiency of the many-core processor. In addition, we demonstrate the potential of the proposed many-core processor by comparing the performance of the many-core processor with that of high-performance CPU and GPU(Graphics Processing Unit). Experimental results indicate that the accuracy result of the SIFT algorithm using the many-core processor was same as that of OpenCV. In addition, the many-core processor outperforms CPU and GPU in terms of execution time. Moreover, this paper proposed an optimal model of the SIFT algorithm on the many-core processor by analyzing energy efficiency and area efficiency for different octave sizes.

• Korean Security Journal
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• no.61
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• pp.377-400
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• 2019

Photography is the most commonly used method of documenting the crime and incident scene as it helps maintaining chain of custody (COC) and prove integrity of the physical evidence. It can also capture phenomena as they are. However, digital images can be manipulated and lose their authenticity as admissible evidence. Thus only limited techniques can be used to enhance images, and one of them is Fourier transform. Fourier transform refers to transformation of images into frequency signals. Fast Fourier transform (FFT) is used in this study. In this experiment, we overlapped fingerprints with graph paper or other fingerprints and separated the fingerprints. Then we evaluated and compared quality of the separated fingerprints to the original fingerprints, and examined whether the two fingerprints can be identified as same fingerprints. In the case of the fingerprints on graph paper and general pattern-overlapping fingerprints, fingerprint ridges are enhanced. On the other hand, in case of separating complicated fingerprints such as core-to-core overlapping and delta-to-delta overlapping fingerprints, quality of fingerprints can be deteriorated. Quality of fingerprints is known to possibly bring negative effects on the credibility of examiners. The result of this study may be applicable to other areas using digital imaging enhancement technology.

• Journal of Information Processing Systems
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• v.8 no.1
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• pp.85-100
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• 2012

The Hartley transform based feature extraction method is proposed for fingerprint matching. Hartley transform is applied on a smaller region that has been cropped around the core point. The performance of this proposed method is evaluated based on the standard database of Bologna University and the database of the FVC2002. We used the city block distance to compute the similarity between the test fingerprint and database fingerprint image. The results obtained are compared with the discrete wavelet transform (DWT) based method. The experimental results show that, the proposed method reduces the false acceptance rate (FAR) from 21.48% to 16.74 % based on the database of Bologna University and from 31.29% to 28.69% based on the FVC2002 database.