• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.304-307
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• 2003

Replacement of aluminum by copper for interconnections in the semiconductor industry has raised a number of important issues. The integration of copper interconnection can be carried out by CMP(chemical mechanical polishing) is used to planarize the surface topography. In this experiments, we evaluated the optimization of several conditions for chemical additives during Cu CMP process. It was presented that the main cause of grown particle size is tartaric acid. The particle size was in inverse propotion to a quantity of bead and the time of milling process. The slurry stabilizer and oxidizer have been shown to have very good effect by addition in later milling process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.625-628
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• 1999

Recently. high-density printed circuit boards(PCB) become indispensable with the minaturization of components. Nickel is deposited on the copper patterns and followed by the gold deposition for improving connection reliability between the printed circuit boards and electronic components. Conventionally electrodeposition has been applied to metalization of copper patterns. However metalization by this method is not applicable for the isolated fine and concentrated patterns. Therefore, metalization technology of the fine patterns by electroless plating is required in place of electrodeposition. The application of electroless nickel plating for interconnection with solder strongly relies on the solderability and the interactions between nickel and solder. Factors such as phosphorus content of the deposit additive and bath temperature may influence solderability of the electroless nickel deposit. So solderability of electroless nickel/ gold deposits was investigated with substrates plated changing the condition of nickel solution.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.32 no.1
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• pp.58-63
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• 2019

Lithium-ion batteries used for IT, automobiles, and industrial energy-storage devices have battery management systems (BMS) to protect the battery from abnormal voltage, current, and temperature environments, as well as safety devices like, current interruption device (CID), fuse, and vent to obtain positive temperature coefficient (PTC). Nonetheless, there are harmful to human health and property and damage the brand image of the manufacturer because of smoke, fire, and explosion of lithium battery packs. In this paper, we propose a systematic protection algorithm combining battery temperature, over-current, and interconnection between protection elements to prevent copper deposition, internal short circuit, and separator shrinkage due to frequent and instantaneous over-current discharges. The parameters of the proposed algorithm are suggested to utilize the experimental data in consideration of battery pack operating conditions and malicious conditions.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.45-50
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• 2006

Copper via filling is the important factor in 3-D stacking interconnection of SiP (system in package). As the packaging density is getting higher, the size of via is getting smaller. When DC electroplating is applied, a defect-free hole cannot be obtained in a small size via hole. To prevent the defects in holes, pulse and pulse reverse current was applied in copper via filling. The holes, $20\and\;50{\mu}m$ in diameter and $100{\sim}190\;{\mu}m$ in height. The holes were prepared by DRIE method. Ta was sputtered for copper diffusion barrier followed by copper seed layer IMP sputtering. Via specimen were filled by DC, pulse and pulse-reverse current electroplating methods. The effects of additives and current types on copper deposits were investigated. Vertical and horizontal cross section of via were observed by SEM to find the defects in via. When pulse-reverse electroplating method was used, defect free via were successfully obtained.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.4
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• pp.47-56
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• 2015

In this paper, the Thermal behavior and reliability characteristics of carbon CCL (Copper Claded Layer), which can be used as the core of HDI (High Density Interconnection) PCB (Printed Circuit Board) are evaluated through experiments and numerical analysis using CAE (Computer Aided Engineering) software. For the characterization of the carbon CCL, it is compared with the conventional FR-4 core and Heavy Cu core. From research results, the deformation amount of the flexure strength of PCB is the highest with pitch grade carbon and thermal behavior of PCB is lowest as temperature increases. In addition, TC (Thermal Cycling), LLTS (Liquid-to-Liquid Thermal Shock) and Humidity tests have been applied in the PCB with carbon core and the reliability of PCB with carbon core is confirmed through reliability tests. Also, possibility of uneven surface of the via hole and wear of the drill bit due to the carbon fibers are analyzed. surface of the via hole is uniform, the surface of the drill bit is smooth. Therefore, it is proved that the carbon CCL has the drilling workability of the same level as conventional core material.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.2
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• pp.29-36
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• 2008

In this paper, mechanical reliability issues of copper through-wafer interconnections are investigated numerically and experimentally. A hermetic wafer level packaging for MEMS devices is developed. Au-Sn eutectic bonding technology is used to achieve hermetic sealing, and the vertical through-hole via filled with electroplated copper for the electrical connection is also used. The MEMS package has the size of $1mm{\times}1mm{\times}700{\mu}m$. The robustness of the package is confirmed by several reliability tests. Several factors which could induce via hole cracking failure are investigated such as thermal expansion mismatch, via etch profile, and copper diffusion phenomenon. Alternative electroplating process is suggested for preventing Cu diffusion and increasing the adhesion performance of the electroplating process. After implementing several improvements, reliability tests were performed, and via hole cracking as well as significant changes in the shear strength were not observed. Helium leak testing indicated that the leak rate of the package meets the requirements of MIL-STD-883F specification.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.136-139
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• 2003

Copper has attractive properties as a multi-level interconnection material due to lower resistivity and higher electromigration resistance as compared with Alumina and its alloy with Copper(0.5%). Among a variety of agents in Copper CMP slurry, $H_2O_2$ has commonly been used as the oxidizer However. $H_2O_2$ is so unstable that it requires stabilization to use as oxidizer Hence, stabilization of $H_2O_2$ is a vital process to get better yield in practical CMP process. In this article the stability of Hydrogen Peroxide as oxidizer of Copper CMP slurry has been investigated. When alumina abrasive was used, $\gamma$-particle Alumina C had a better stability than $\alpha$-particle abrasive. As adding KOH as pH buffering agent, $H_2O_2$ stability in slurry decreased. Urea hydrogen peroxide was used as oxidizer, an enhanced stability was gotten. When $H_3PO_4$ as $H_2O_2$ stabilizer was added, the decrease of $H_2O_2$ concentration in slurry became slower. Even though adding $H_2O_2$ in slurry after bead milling lead to better stability than in advance of bead milling, it had a lower dispersibility.

• Journal of Welding and Joining
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• v.16 no.4
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• pp.92-97
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• 1998

Because of the low melting temperature of solder, each temperature cycle initiates an irrecoverable creep deformation at the solder interconnection which connects the package body with the PCB. The crack starts and propagates from the position where the creep deformation is maximized. This work has tried to compare and analyze the thermal fatigue life of solder interconnection which is affected by the lead material, the size of die pad, chip thickness, and interface delamination of 48-Pin TSOP under the temperature cycle ($0^{\circ}C$~1$25^{\circ}C$). The crack initiation position and thermal fatigue life which are calculated by using FEA method are well matched with the results of experiments. The thermal Fatigue life of copper lead frame is extended around 3.6 times longer than that of alloy 42 lead frame. It is maximized when the chip size is matched with the length of the lead. It tends to be extended as the thickness of chip got thinner. As the interfacial delamination between die pad and EMC is increased, the thermal fatigue life tends to decrease in the beginning of delamination, and increase after the delamination grew after 45% of the length of die pad.

• Journal of Information Processing Systems
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• v.14 no.1
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• pp.270-279
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• 2018

PCI Express (PCIe) bus, which was only used as an internal I/O bus of a computer system, has expanded its function to outside of a system, with progress of PCIe switching processor. In particular, advanced features of PCIe switching processor enable PCIe bus to serve as an interconnection network as well as connecting external devices. As PCIe switching processors more advanced, it is required to consider the different adapter card architecture. This study developed multipurpose adapter cards by applying an on-board optical module, a latest optical communications element, in order to improve transfer distance and utilization. The performance evaluation confirmed that the new adapter cards with long cable can provide the same bandwidth as that of the existing adapter cards with short copper cable.