• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.5
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• pp.1829-1846
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• 2021

Transient faults occur in computation units of a processor, which can cause control flow errors (CFEs) and compromise system reliability. The software-based methods perform illegal control flow detection by inserting redundant instructions and monitoring signature. However, the existing methods not only have drawbacks in terms of performance overhead, but also lack of configurability. We propose a configurable approach CCFCA for detecting CFEs. The configurability of CCFCA is implemented by analyzing the criticality of each region and tuning the detecting granularity. For critical regions, program blocks are divided according to space-time overhead and reliability constraints, so that protection intensity can be configured flexibly. For other regions, signature detection algorithms are only used in the first basic block and last basic block. This helps to improve the fault-tolerant efficiency of the CCFCA. At the same time, CCFCA also has the function of solving confusion and instruction self-detection. Our experimental results show that CCFCA incurs only 10.61% performance overhead on average for several C benchmark program and the average undetected error rate is only 9.29%. CCFCA has high error coverage and low overhead compared with similar algorithms. This helps to meet different cost requirements and reliability requirements.

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.43.6-43
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• 2002

$\textbullet$ KAEROT/m1 with an omni-directional planetary wheel mechanism for the narrow corridor. $\textbullet$ KAEROT/m2 can pass over the ditch with specially designed four wheel of a re-configurable crawler. $\textbullet$ Stereo imaging system with master manipulator enhancing the tele-presence. $\textbullet$ Small hybrid dosimeter detecting radiation dose and dose rate simultaneously.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.767-769
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• 2002

A novel RE configurable device composed by bare-chip, bumps and board are proposed. We call this "Field-Programmable RF Gate Array (FPRA)," This device, a kind of programmable system packages, has a potential to be applied to wireless communication terminals such as software-defined radio.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.924-927
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• 2002

In this paper we proposed the design space exploration environment of re-configurable hybrid systems and evaluate the performance by changing design parameters. With this, we analyzed the effect of various scheduling methods which determine how we allocate hardware/software resources to application program. A simple static (fixed) mapping strategy produces almost the same performance compared with a sophisticated dynamic mapping strategy especially when a CPU is already busy with its pre-assigned own tasks.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.381-384
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• 2001

This paper describes the features and development of a RAM compiler that can generate low power, high speed, synchronous CMOS SRAM. The compiled SRAM can be configurable from 64bytes to 16Kbytes in one bank and has 2ns access time typically. Basic cells are developed using 2-poly, 4-metal 0.35um CMOS technology. This SRAM compiler is developed using SKIL $L^{TM}$ language and generates layout and schematic in Cadence environment.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.357-360
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• 2001

As SOC design methodology becomes popular, processors, the essential core in embedded system are required to be designed fast and supported to customers with expansive behavior description. This paper presents new methodology to meet such goals with designer configurable instruction set simulator for processors. This paper proposes new language called PML(Processor Modeling Language), which is based on microprogramming scheme and is also successful in most behavior of processors. By using this, we can describe scalar processor very efficiently with by-far faster simulation speed in compared with HDL model.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.422-425
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• 2003

Software reconfigurable radio will give future users a number of benefits like global roaming, multi mode, multi band, and multi standard. It will also offer complete programmability and reconfigurability to both multi mode and multi functional communication terminal and network nodes. This configuration will be implemented by application of different combination of radio configurable software. In this paper, It proposes the algorithm needed for reconfiguration with basic explanation of the software download. A description of an implementation such reconfiguration processes as partial download and full download and critical and non-critical download installation using the registration table in included.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2002.12a
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• pp.379-382
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• 2002

GA(Genetic Algorithm)는 자연계 진화를 모방한 계산 알고리즘으로서 단순하고 응용이 쉽기 때문에 여러 분야에 사용되고 있다. 하지만 GA의 단점은 일반적인 소프트웨어로 동작시켰을 때는 실행속도가 느리다는 것이다. 특히 chromosome이 길 경우 연속적인 교차, 돌연변이를 수행해야한다. GA Processor(GAP)는 GA를 수행하기위한 전용 Processor로서 GA의 동작을 빨리 수행할 수 있게 한다. 본 논문에서는 pipeline 구조의 GAP를 설계하여 GA를 수행함에 있어 소프트웨어와 하드웨어의 성능을 비교한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.761-764
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• 2006

We have developed a new remote-configurable firewall system that provides secure and easy-to-use access to home-network appliances such as network cameras, PVRs, and home file servers, through the internet. With a simple web browser operation, remote users can dynamically open and close the firewall of the home gateway. The firewall rule creation is based on an authentication of the remote client, and thus only packets from the authorized client can pass through the firewall, we analyses the sorority design for home gateway in ubiquitous surroundings.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11A
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• pp.936-944
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• 2003

In this paper, we propose an AND/XOR-based technology mapping method for field programmable gate arrays (FPGAs). Due to the fixed size of the programmable blocks in an FPGA, decomposing a circuit into sub-circuits with appropriate number of inputs can achieve excellent implementation efficiency. Specifically, the proposed technology mapping method is based on Davio expansion theorem to decompose a given Boolean circuit. The AND/XOR nature of the proposed method allows it to operate on XOR intensive circuits, such as error detecting/correcting, data encryption/decryption, and arithmetic circuits, efficiently. We conduct experiments using MCNC benchmark circuits. When using the proposed approach, the number of CLBs (configurable logic blocks) is reduced by 67.6% (compared to speed-optimized results) and 57.7% (compared to area-optimized results), total equivalent gate counts are reduced by 65.5 %, maximum combinational path delay is reduced by 56.7 %, and maximum net delay is reduced by 80.5 % compared to conventional methods.