• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.9A
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• pp.763-773
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• 2003

In this paper, we present a register renaming method for conditional execution out-of-order instruction issue microprocessors. Register renaming method reduces false data dependencies (write after read(WAR) and write after write(WAW)). To implement a conditional execution out-of-order instruction issue microprocessor using register renaming, we use a register file which includes both in-order state physical registers and look-ahead state physical registers to share all logical registers. And we design an in-order state indicator, a renaming state indicator, a physical register assigning indicator, a condition prediction buffer and a reorder buffer. As we utilize the above hardwares, we can do register renaming and trace the in-order state. In this paper, we present an improved register renaming method using smaller hardware resources than conventional register renaming method. And this method eliminates an associative lookup and provides a short recovery time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.10
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• pp.23-32
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• 2007

This paper proposes a reconfigurable parallel processor architecture which can efficiently implement various multimedia applications, such as 3D graphics, H.264/H.263/MPEG-4, JPEG/JPEG2000, and MP3. The proposed architecture directly connects memories and processors so that memory access time and power consumption are reduced. It supports floating-point operations needed in the geometry stage of 3D graphics. It adopts partitioned SIMD to reduce hardware costs. Conditional execution of instructions is used for easy development of parallel algorithms.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.2
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• pp.196-204
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• 1996

This paper presents a new scheduling algorithm, which is the most improtant subtask in the high level synthesis. The proposed algorithm performs scheduling in consideration of resource sharing concept based on characteristics of conditionsla bransches in the intermediate data structure. CDFG (control data flow graph) generated by a VHDL analyzer. This algorithm constructs a conditon graph based on time frame of each operation using both the ASAP and the ALAP scheduling algorithm. The conditon priority is obtained from the condition graph constructed from each conditional brance. The determined condition priority implies the sequential order of transforming the CDFG with conditonal branches into the CDFG without conditional branches. To minimize resource cost, the CDFG with conditional branches are transformed into the CDFG without conditonal brancehs according to the condition priority. Considering the data dependency, the hardware constraints, and the data execution time constraints, each operation in the transformed CDFG is assigned ot control steps. Such assigning of unscheduled operations into contorl steps implies the performance of the scheduling in the consecutive movement of operations. The effectiveness of this algorithm is hsown by the experiment for the benchmark circuits.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.24 no.3
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• pp.437-444
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• 2014

In this paper, we introduce a Graph based Binary Code Execution Path Exploration Platform. In the graph, a node is defined as a conditional branch instruction, and an edge is defined as the other instructions. We implemented prototype of the proposed method and works well on real binary code. Experimental results show proposed method correctly explores execution path of target binary code. We expect our method can help Software Assurance, Secure Programming, and Malware Analysis more correct and efficient.

• The Transactions of the Korea Information Processing Society
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• v.2 no.2
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• pp.264-276
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• 1995

In this paper, a technique for eliminating conditional branches in the compilers for superscalar processors is presented. The technique consists of three major steps. The first step transforms conditional branches into equivalent expressions using algebraic laws. The second step searches all possible instruction sequences for those expressions using GSO of Granlund/Kenner. Finally an optimal sequence that has the least dynamic count for the target superscalar processor is selected from the GSO output. Experiment result shows that for each conditional branch is the input program matched by one of the optimization patterns, the proposed technique outperforms more than 25% speedup of execution time over the original code when the GNU C compiler and the SuperSPARC processor are used.

• The Transactions of the Korea Information Processing Society
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• v.1 no.1
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• pp.38-49
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• 1994

One of the most common problems encountered in the automatic translation of FORTRAN source code to VECTRAN is the occurrence of conditional transfer of control within loops. Transfers of control create control dependencies, in which the execution of a statement is dependent on the value of a variable in another statement. In this paper I propose algorithms involve an attempt to convert statements in the loop into conditional assignment statements that can be easily analyzed for data dependency, and this paper presents a simplification method for conditional assignment statement. Especially, I propose not only a method for simplifying boolean functions but extended method for n-state functions.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.6
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• pp.1365-1376
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• 1997

In this paper, we designed real time mechanism control language and proposed execution time analysis technique. It was impossible to handle real-time mechanism control programs like programmable controller, numerical controller, distributed control system and robot controller with general purpose programming languages and operating systems because they have to process electric signals generated by thousands of sensors at the same at the same time and in real time. So we made it possible to predict plausibility of time constraint constructs of tiem constraint construct of a real time application program at compilation time by adding time constraint constructs and mechanism synchronization structure to conditional statement and iteration statement of a programming language and developing execution time analysis technique.

• ETRI Journal
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• v.37 no.5
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• pp.1012-1022
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• 2015

Conventional cryptographic algorithms are not sufficient to protect secret keys and data in white-box environments, where an attacker has full visibility and control over an executing software code. For this reason, cryptographic algorithms have been redesigned to be resistant to white-box attacks. The first white-box AES (WB-AES) implementation was thought to provide reliable security in that all brute force attacks are infeasible even in white-box environments; however, this proved not to be the case. In particular, Billet and others presented a cryptanalysis of WB-AES with 230 time complexity, and Michiels and others generalized it for all substitution-linear transformation ciphers. Recently, a collision-based cryptanalysis was also reported. In this paper, we revisit Chow and others's first WB-AES implementation and present a conditional re-encoding method for cryptanalysis protection. The experimental results show that there is approximately a 57% increase in the memory requirement and a 20% increase in execution speed.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.723-724
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• 2006

Exploiting the instruction level parallelism encountered with the limit. Single chip multiprocessor was introduced to overcome the limit of traditional processor using the instruction level parallelism. Also, a branch miss prediction is one of the causes that reduce the processor performance. In order to overcome the problems, in this paper, we make single chip multiprocessor having the idle core execute the two control flow of conditional branch. This scheme is a kind of multi-path execution technique based on single chip multiprocessor architecture.

• Proceedings of the Korean Information Science Society Conference
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• 2004.10a
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• pp.544-546
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• 2004

조건부 실행 명령어는 분기명령어의 사용을 줄여 분기 명령어 예측 실패로 인한 프로세서의 성능 저하를 막을 수 있다. 하지만 조건부 실행 명령어는 순차적 프로세서를 위하여 설계되었기 때문에, 고성능 비순차적 프로세서에서는 적용할 수 없었다. 본 논문에서는 기존의 슈퍼스칼라 프로세서 구조를 최소한의 변경을 통하여 조건부 실행 명령어의 비순차 실행을 지원하는 구조를 제안한다. 또한 제안된 구조를 시뮬레이션 할 수 있는 시뮬레이터를 작성 성능을 검증하였다. 그 결과 제안된 구조를 통하여 프로세서의 성능을 27% 이상 향상시킬 수 있다