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A Reconfigurable Parallel Processor for Efficient Processing of Mobile Multimedia  

Yoo, Se-Hoon (School of Electrical and Computer Engineering, University of Seoul)
Kim, Ki-Chul (School of Electrical and Computer Engineering, University of Seoul)
Yang, Yil-Suk (U-Terminal Research Team, Electronics and Telecommunications Research Institute)
Roh, Tae-Moon (U-Terminal Research Team, Electronics and Telecommunications Research Institute)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.44, no.10, 2007 , pp. 23-32 More about this Journal
Abstract
This paper proposes a reconfigurable parallel processor architecture which can efficiently implement various multimedia applications, such as 3D graphics, H.264/H.263/MPEG-4, JPEG/JPEG2000, and MP3. The proposed architecture directly connects memories and processors so that memory access time and power consumption are reduced. It supports floating-point operations needed in the geometry stage of 3D graphics. It adopts partitioned SIMD to reduce hardware costs. Conditional execution of instructions is used for easy development of parallel algorithms.
Keywords
Parallel processor; multimedia; mobile; SIMD; conditional execution;
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Times Cited By KSCI : 1  (Citation Analysis)
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