• Journal of the Korean Mathematical Society
• /
• v.36 no.5
• /
• pp.945-958
• /
• 1999

Let E be an elliptic curve over with complex multiplication. Suppose that E is defined over F= (j(E)). We study possible degrees of F-isogenies of E.

• ETRI Journal
• /
• v.32 no.1
• /
• pp.1-10
• /
• 2010

In this paper, we present a fast Fourier transform (FFT) processor with four parallel data paths for multiband orthogonal frequency-division multiplexing ultra-wideband systems. The proposed 128-point FFT processor employs both a modified radix-$2^4$ algorithm and a radix-$2^3$ algorithm to significantly reduce the numbers of complex constant multipliers and complex booth multipliers. It also employs substructure-sharing multiplication units instead of constant multipliers to efficiently conduct multiplication operations with only addition and shift operations. The proposed FFT processor is implemented and tested using 0.18 ${\mu}m$ CMOS technology with a supply voltage of 1.8 V. The hardware- efficient 128-point FFT processor with four data streams can support a data processing rate of up to 1 Gsample/s while consuming 112 mW. The implementation results show that the proposed 128-point mixed-radix FFT architecture significantly reduces the hardware cost and power consumption in comparison to existing 128-point FFT architectures.

• Journal for History of Mathematics
• /
• v.15 no.3
• /
• pp.17-24
• /
• 2002

It will be described the discovery of fundamental algebras such as complex numbers and the quaternions. Cardano(1539) was the first to introduce special types of complex numbers such as 5$\pm$$\sqrt{-15}$. Girald called the number a$\pm$$\sqrt{-b}$ solutions impossible. The term imaginary numbers was introduced by Descartes(1629) in “Discours la methode, La geometrie.” Euler knew the geometrical representation of complex numbers by points in a plane. Geometrical definitions of the addition and multiplication of complex numbers conceiving as directed line segments in a plane were given by Gauss in 1831. The expression “complex numbers” seems to be Gauss. Hamilton(1843) defined the complex numbers as paire of real numbers subject to conventional rules of addition and multiplication. Cauchy(1874) interpreted the complex numbers as residue classes of polynomials in R[x] modulo $x^2$＋1. Sophus Lie(1880) introduced commutators [a, b] by the way expressing infinitesimal transformation as differential operations. In this paper, it will be studied general quaternion algebras to finding of algebraic structure in Algebras.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• v.9 no.1
• /
• pp.925-927
• /
• 2005

The study is about a finite field multiplying unit, which performs a calculation t-times as fast as the Mastrovito's multiplier architecture, suggesting and using the 2-times faster multiplier architecture. Former studies on finite field multiplication architecture includes the serial multiplication architecture, the array multiplication architecture, and the hybrid finite field multiplication architecture. Mastrovito's serial multiplication architecture has been regarded as the basic architecture for the finite field multiplication, and in order to exploit parallelism, as much resources were expensed to get as much speed in the finite field array multipliers. The array multiplication architecture has weakness in terms of area/performance ratio. In 1999, Parr has proposed the hybrid multipcliation architecture adopting benefits from both architectures. In the hybrid multiplication architecture, the main hardware frame is based on the Mastrovito's serial multiplication architecture with smaller 2-dimensional array multipliers as processing elements, so that its calculation speed is fairly fast costing intermediate resources. However, as the order of the finite field, complex integers instead of prime integers should be used, which means it cannot be used in the high-security applications. In this paper, we propose a different approach to devise a finite field multiplication architecture using Mastrovito's concepts.

• Journal of the Chungcheong Mathematical Society
• /
• v.34 no.4
• /
• pp.317-326
• /
• 2021

Let K be an imaginary quadratic field other than ℚ(${\sqrt{-1}}$) and ℚ(${\sqrt{-3}}$), and let 𝒪_K be its ring of integers. Let N be a positive integer such that N = 5 or N ≥ 7. In this paper, we generate the ray class field modulo N𝒪_K over K by using a single x-coordinate of an elliptic curve with complex multiplication by 𝒪_K.

• Journal of information and communication convergence engineering
• /
• v.11 no.2
• /
• pp.112-117
• /
• 2013

In order to reuse a register transfer level (RTL)-based IP block, it takes another architectural exploration in which the RTL will be put, and it also takes virtual platforms to develop the driver and applications software. Due to the increasing demands of new technology, the hardware and software complexity of organizing embedded systems is growing rapidly. Accordingly, the traditional design methodology cannot stand up forever to designing complex devices. In this paper, I introduce an electronic system level (ESL)-based approach to designing complex hardware with a derivative of SystemVerilog. I adopted the concept of reuse with higher levels of abstraction of the ESL language than traditional HDLs to design multiplication server farms. Using the concept of ESL, I successfully implemented server farms as well as a test bench in one simulation environment. It would have cost a number of Verilog/C simulations if I had followed the traditional way, which would have required much more time and effort.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.11 no.3
• /
• pp.270-276
• /
• 2018

This paper presents a low area 256-point pipelined FFT architecture, especially for IEEE 802.16a WiMAX systems. Radix-24 algorithm and single-path delay feedback (SDF) architecture are adopted in the design to reduce the complexity of twiddle factor multiplication. A new cascade canonical signed digit (CSD) complex multipliers are proposed for twiddle factor multiplication, which has lower area and less power consumption than conventional complex multipliers composed of 4 multipliers and 2 adders. Also, the proposed cascade CSD multipliers can remove look-up table for storing coefficient of twiddle factors. In hardware implementation with Cyclone 10LP FPGA, it is shown that the proposed FFT design method achieves about 62% reduction in gate count and 64% memory reduction compared with the previous schemes.

• Communications of the Korean Mathematical Society
• /
• v.6 no.1
• /
• pp.27-30
• /
• 1991

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.22 no.5
• /
• pp.999-1007
• /
• 2012

Multi-precision multiplication over public key cryptography should be considered for performance enhancement due to its computational complexity. Particularly, embedded device is not suitable to execute high complex computation, public key cryptography, because of its limited computational power and capacity. To overcome this flaw, research on multi-precision multiplication with fast computation and small capacity is actively being conducted. In the paper, we explore the cutting-edge technology of multi-precision multiplication for efficient implementation of public key cryptography over sensor network. This survey report will be used for further research on implementation of public key cryptography over sensor network.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.2
• /
• pp.29-37
• /
• 1997

A new algorithm and parallel architecture for high-speed complex number multiplication is presented, and a prototype chip based on the proposed approach is designed. By employing redundant binary (RB) arithmetic, an N-bit complex number multiplication is simplified to two RB multiplications (i.e., an addition of N RB partial products), which are responsible for real and imaginary parts, respectively. Also, and efficient RB encoding scheme proposed in this paper enables to generate RB partial products without additional hardware and delay overheads compared with binary partial product generation. The proposed approach leads to a highly parallel architecture with regularity and modularity. As a results, it results in much simpler realization and higher performance than the classical method based on real multipliers and adders. As a test vehicle, a prototype 8-b complex number multiplier core has been fabricated using $0.8\mu\textrm{m}$ CMOS technology. It contains 11,500 transistors on the area of about $1.05 \times 1.34 textrm{mm}^2$. The functional and speed test results show that it can safely operate with 200 MHz clock at $V_{DD}=2.5 V$, and consumes about 90mW.