• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.1
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• pp.22-28
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• 2009

This paper presents a fast received signal strength indicator (RSSI) circuit for wireless communication application. The proposed circuit is developed using power detectors and an analog-to-digital converter to achieve a fast settling time. The power detector is consisted of a novel logarithmic variable gain amplifier (VGA), a peak detector, and a comparator in a closed loop. The VGA achieved a wide logarithmic gain range in a closed loop form for stable operation. For the peak detector, a fast settling time and small ripple are obtained using the orthogonal characteristics of quadrature signals. In $0.18-{\mu}m$ CMOS process, the RSSI value settles down in $20{\mu}s$ with power consumption of 20 mW, and the maximum ripple of the RSSI is 30 mV. The proposed RSSI circuit is fabricated with a personal handy-phone system transceiver. The active area is $0.8{\times}0.2\;mm^2$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.395-404
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• 2016

A 6-bit 3.4 GS/s flash ADC in a 65 nm CMOS process is reported along with the proposed 4x time-domain interpolation technique which allows the reduction of the number of comparators from the conventional $2^N-1$ to $2^{N-2}$ in a N-bit flash ADC. The proposed scheme effectively achieves a 4x interpolation factor with simple SR-latches without extra clocking and calibration hardware overhead in the interpolated stage where only offset between the $2^{N-2}$ comparators needs to be calibrated. The offset in SR-latches is within ${\pm}0.5$ LSB in the reported ADC under a wide range of process, voltage supply, and temperature (PVT). The design considerations of the proposed technique are detailed in this paper. The prototype achieves 3.4 GS/s with 5.4-bit ENOB at Nyquist and consumes 12.6 mW power at 1 V supply, yielding a Walden FoM of 89 fJ/conversion-step.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.48-57
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• 2013

This paper presents a power management system of the dye-sensitized solar cell (DSSC) for ubiquitous sensor network (USN) applications. The charge pump with a luminance-controlled oscillator regulates the load impedance of the DSSC to track the maximum power point (MPP) under various light intensities. The low drop-out regulator with a hysteresis comparator supplies intermittent power pulses that are wide enough for USN to communicate with a host transponder even under dim light conditions. With MPP tracking, approximately 50% more power is harvested over a wide range of light intensity. The power management system fabricated using $0.13{\mu}m$ CMOS technology works with DSSC to provide power pulses of $36{\mu}A$. The duration of pulses is almost constant around $80{\mu}s$ (6.5 nJ/pulse), while the pulse spacing is inversely proportional to the light intensity.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.148-149
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• 2008

As infrared light is radiated, the CMOS Readout IC (ROIC) for the microbolometer type infrared sensor detects voltage or current when the resistance value in the bolometer sensor varies. One of the serious problems in designing the ROIC is that resistances in the bolometer and reference resistor have process variation. This means that each pixel does not have the same resistance, causing serious fixed pattern noise problems in sensor operations. In this paper, Reference resistor compensation technique was proposed. This technique is to compensate the reference resistance considering the process variation, and it has the same reference resistance value as a bolometer cell resistance by using a comparator and a cross coupled latch.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.57 no.2
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• pp.153-159
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• 2008

We have developed an absolute evaluation method to obtain the ratio error and phase displacement of a current transformer (CT) without any precise standard CT by measuring four parameters in a CT equivalent circuit. The excitation admittance in the CT equivalent circuit can be obtained by employing standard resistors with negligible reactive component. The secondary leakage impedance in the CT equivalent circuit can be measured using a universal impedance bridge. The method was applied to CTs under test with the wide current ratios in the range of 5 A / 5 A - 5,000 A / 5 A and 5 A / 1 A - 5,000 A / 1 A. The ratio error and phase displacement of the CT under test obtained in this study are consistent with those measured at the national institute in Canada using the same CT under test within an expanded uncertainty (k = 2) in the overall current ratios.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.57 no.2
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• pp.164-169
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• 2008

National standard system for calibrating voltage transformer(VT) up to primary voltage of 240 kV have been established in 2005. The system consists of voltage source, regulating unit, VT testing unit, standard VT, VT under test and VT burden. To verify and validate the performance for 240 kV VT calibration system, the comparison with the National Measurement Institute of Australia(NMIA) has been performed using same VTs. The comparison results of the VTs mesured at the Korea Research Institute of Stansdards and Science(KRISS) are consistent with those measured at NMIA within 0.002 % for ratio error and 0.14 min for phase displacement in the primary voltage ranges of Vp = 3300 V - 22000 V with a secondary voltage of Vs = 110 V.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.3
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• pp.395-400
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• 2013

In this paper, we introduce the implementation of high accurate level sensor system using the pulse wave type magnetostriction sensor. When a current pulse flows along the waveguide, the magnetic field also propagates towards the end of waveguide. When this magnetic field just passes the position of the magnet for level detection, the resultant magnetic field by these two magnetic fields makes a torsional reflected signal. This is used to calculate the time difference between a interrogation pulse wave and this torsional reflected signal. The key elements and characteristics were investigated to implement level sensor system based on this principle. We introduce a method to calculate the speed of ultrasonic reflected signal and how to make a model of sensing coil. In particular, we experiment with the characteristics of the torsional reflected signal according to the changes of the interrogation voltage and displacement. To make high accurate level sensor system, two methods were compared. One is to use the comparator and time counter, the other is STFT(Short Time FFT) which is capable of the time-frequency analysis.

• ETRI Journal
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• v.36 no.6
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• pp.905-912
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• 2014

In this paper, a new architecture is proposed to achieve complexity efficiency in implementing variable pulse position modulation (VPPM). VPPM, specified in IEEE 802.15.7, can support wireless communication and dimming control simultaneously using visible light. The proposed architecture is based on the VPPM signal property in which the transition point of the modulated output is obtained by counting the sample index and comparing it to both the assigned dimming factor and the transmitting data. Therefore, the proposed architecture can be composed of simple logics, including a counter, a comparator, and an inverter, all of which are insensitive to the dimming resolution in contrast to a conventional codeword-table method. This paper describes the verification of the proposed algorithm through a register-transfer level implementation of the codeword and proposed architectures. In comparison with the codeword-table method, the proposed method gains a nine-fold complexity reduction at a 1% dimming-step resolution.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.7 no.4
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• pp.125-132
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• 1987

The bundle adjustment used in photogrammetric data reduction is based on the collinearity condition. Photogrammetry has been used in many non-topographic applications. Due to the necessities of having fiducial marks and knowing initial approximations for interior and exterior orientation elements in bundle adjustment, it cannot be applied when non-metric cameras are used. Marzan and Karara develop the DLT(Direct Linear Transformation) program which directly transforms comparator coordinates into object space coordinates without approximate values. In this paper, several modifications of original DLT program have been made for accuracy improvement in close-range photogrammetry using non-metric cameras. In modified program, gross error detection method and computation of exterior orientation elements are incorporated, and more iterations are introdued.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.104-110
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• 2011

A CMOS Image Sensor (CIS) mounted on mobile appliances requires low power consumption due to limitations of the battery life cycle. In order to reduce the power consumption of CIS, we propose novel power reduction techniques such as a data flip-flop circuit with leakage current elimination and a low power single slope analog-to-digital (A/D) converter with a sleep-mode comparator. Based on 0.13 ${\mu}m$ CMOS process, the chip satisfies QVGA resolution (320 ${\times}$ 240 pixels) that the cell pitch is 2.25 um and the structure is a 4-Tr active pixel sensor. From the experimental results, the performance of the CIS has a 10-b resolution, the operating speed of the CIS is 16 frame/s, and the power dissipation is 25 mW at a 3.3 V(analog)/1.8 V(digital) power supply. When we compare the proposed CIS with conventional ones, the power consumption was reduced by approximately 22% in the sleep mode, and 20% in the active mode.