• JSTS:Journal of Semiconductor Technology and Science
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• 제17권1호
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• pp.29-34
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• 2017

A CMOS-based temperature sensor is proposed for low-voltage and low-power on-chip thermal monitoring applications. The proposed temperature sensor converts a proportional to absolute temperature (PTAT) current to a PTAT frequency using an integrator and hysteresis comparator. In addition, it operates in the subthreshold region, allowing reduced power consumption. The proposed temperature sensor was fabricated in a standard 90 nm CMOS technology. Measurement results of the proposed temperature sensor show a temperature error of between -0.81 and $+0.94^{\circ}C$ in the temperature range of 0 to $70^{\circ}C$ after one-point calibration at $30^{\circ}C$, with a temperature coefficient of $218Hz/^{\circ}C$. Moreover, the measured energy of the proposed temperature sensor is 36 pJ per conversion, the lowest compared to prior works.

• 한국통신학회논문지
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• 제31권1A호
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• pp.58-64
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• 2006

900 MHz 대역의 ISO-18000-6B형 표준의 수동형 RFID 리더용 트랜시버를 개발하였다. 송신부의 ASK 변조회로는 GaAs SPST 스위치를 이용하여 고속 저전력 변조 회로로 구성하였으며, 수신부에서는 이중 평형 믹서와 비교기를 이용하여 복조회로를 구성하였다. LO 신호에 대한 우수 고조파 성분들을 억압하고 수신기의 선형성을 향상시키기 위하여 연산 증폭기를 이용한 복조회로와 전압 플로워 및 비교기를 사용하여 회로의 복잡성을 개선하였다. 개발된 트랜시버는 $900{\sim}916\;MHz$ 대역에서 6 dBi의 상용 안테나를 사용하여 5 m의 인식 거리를 얻었다.

• 한국정보통신학회논문지
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• 제7권6호
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• pp.1297-1303
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• 2003

반도체 방식의 capacitive type 지문인식센서의 신호처리를 위한 개선된 회로를 설계하였다. 최 상위 sensor plate가 지문의 굴곡을 감지한 capacitance의 변화를 전압의 신호로 전환하기위해서 charge-sharing 방식의 회로를 적용하였다. 지문센서 감도저하의 가장 큰 원인인 sensor plate에 존재하는 parasitic capacitance를 최소화하고 ridge와 valley 사이의 전압차를 향상시키기 위하여 기존과는 다른 아날로그버퍼회로를 설계하였다. 센서전압과 기준전압 신호를 비교하기 위해서 비교기를 설계하였으며, 센서어레이의 수직, 수평간 isolation 대책을 통하여 ESD 및 노이즈방지를 위한 설계를 제안하였다. 제안된 신호처리회로는 128${\times}$l44 pixel 규모의 회로로 구현되었다. 본 설계회로는 향후 생체인식을 이용한 정보보호용 지문인식 시스템에 응용될 수 있으리라본다.

• 한국정보통신학회논문지
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• 제13권5호
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• pp.1030-1037
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• 2009

현재 SAW 센서는 많은 발전을 해왔고 온도나 압력용 SAW 센서를 저전력, 고속 신호 처리로 하기 위해서는 TDS(Time Domain Sampling) 방식을 이용한 리더기 플랫폼이 필요하다. 이러한 리더기를 제작하기 위해서는 SAW 센서의 표준 응답신호와의 변화된 응답시간과의 짧은 시간차를 측정하기 위해 고속의 타이머가 필요하게 된다. 여기서 제안하는 플랫폼은 SAW 센서에 신호를 받아서 비교기로 아날로그 신호를 디지털 신호로 전환하여 그 전환된 신호를 타이머 모듈에서 읽어 들여 신호들의 시간차를 측정하여 표시하여 나노초(Nano Second) 단위의 시간을 측정하는 방법을 제안 하고자 한다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.334-337
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• 2002

The Quantum Hall Resistance(QHR) device which consists of GaAs/AlGaAs heterojunction structure is used for the realization of QHR Standard based on QHE. In order to characterize electrical contact resistances and dissipations of the device, it is slowly cooled down for eliminating thermal shock and unwanted noise. Then, the two properties are measured under 1.5 K and 5.15 T. Contact resistances are all within 1.2 Ω and longitudinal resistivities are all within 1 mΩ up to DC 90${\mu}$A. The results mean the device is operated well to realize the QHR Standard. To confirm it, the QHR Standard having the device is compared using a direct current comparator bridge with a 1 Ω resistance standard which the calibrated value is known from QHR standards maintained by other countries. The difference between them is agreed well within measurement uncertainty. It is thus considered that the properties of the device is estimated well and has good performance.

• Journal of Electrical Engineering and Technology
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• 제1권1호
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• pp.63-72
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• 2006

The purpose of this raper is to address the negative impedance instability in DC/DC converters. We present the negative impedance instability of PWM DC/DC converters loaded by constant power loads (CPLs). An approach to design digital controllers for DC/DC converters Is presented. The proposed method, called Power Alignment control technique, is applied to DC/DC step-down choppers operating in continuous conduction or discontinuous conduction modes with CPLs. This approach uses two predefined state variables instead of conventional pulse width modulation (PWM) to regulate the output voltage. A comparator compares actual output voltage with the reference and then switches between the appropriate states. It needs few logic gates and comparators to be implemented thus, making it extremely simple and easy to develop using a low-cost application specific integrated circuit (ASIC) for converters with CPLs. Furthermore, stability of the proposed controllers using the small signal analysis as well as the second theorem of Lyapunov is verified. Finally, simulation and analytical results are presented to describe and verify the proposed technique.

• 대한전기학회논문지:전력기술부문A
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• 제53권7호
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• pp.365-374
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• 2004

The relay measures the frequency of the power system in order to detect faults and separate them from the system. Many estimation algorithms for the relay have been proposed to accurately measure the frequency. This paper proposes a new frequency measurement method using the digital phase locked-loop(DPLL) for the relay of the power system. The proposed method is configured with a DPLL scheme and verified through computer simulations and experimental tests. In order to cope with noises in the power system, filters are included in the input signal processing part and the frequency comparator. MATLAB is used for computer simulations and an experimental setup with a CPU and an FPGA(Field Programmable Gate Array) is constructed. The loop filter of the DPLL is run in the CPU software In adjust parameters and others are in the FPGA. Experimental tests are performed lot a function generator and the power system. Results show that the proposed method is appropriate to the frequency measurement for the relay.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.565-566
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• 2008

The high efficiency power management IC(PMIC) for Moblie application is proposed in this paper. PMIC is controlled with PWM control method in order to have high power efficiency at high current level. The saw-tooth generator is made to have 1.2 MHz oscillation frequency and full range of output swing from ground to supply voltage(VDD:3.3V). The comparator is designed with two stage OP amplifier. And the error amplifier has 70dB DC gain and $64^{\circ}$ phase margin. DC-DC converter, based on Voltage-mode PWM control circuits, achieved the high efficiency near 95% at 100mA output current. DC-DC converter is designed with LDO in stand-by mode which fewer than 1mA for high efficiency.

• 전기전자학회논문지
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• 제22권2호
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• pp.316-323
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• 2018

본 논문에서는 가시광통신에서 플리커를 방지하기 위한 3-레벨 바이트반전 전송방식을 새로이 소개한다. 가시광 송신부에서는 3-레벨 LED 변조기를 사용하여 원신호와 반전신호를 차례로 전송하며, 데이터 전송과정에서 LED의 평균광출력이 일정하게 유지되어 플리커가 발생하지 않는다. 가시광 수신부에서는 간단한 비교기를 사용하여 원신호가 쉽게 복구된다. 이 방식에서는 플리커 방지를 위하여 별도의 클럭이나 캐리어가 필요하지 않아 구조가 매우 간단하며, 저렴한 비용으로 플리커가 없는 실내의 가시광 시스템을 구축하는 데에 유용할 것으로 판단된다.

• 제어로봇시스템학회논문지
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• 제20권7호
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• pp.756-759
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• 2014

DC/DC converters are commonly used to generate regulated DC output voltages with high-power efficiencies from different DC input sources. The converters can be applied in the regenerative braking of DC motors to return energy back to the supply, resulting in energy savings for the systems at periodic intervals. The fundamental converter studied here consists of an IGBT (Insulated Gate Bipolar mode Transistor), an inductor, a capacitor, a diode, a PWM-IC (Pulse Width Modulation Integrated Circuit) controller with oscillator, amplifier, and comparator. The PWM-IC is a core element and delivers the switching waveform to the gate of the IGBT in a stable manner. Display of the DC/DC converter output depends on the IGBT's changes in the threshold voltage and PWM-IC's pulse width. The simulation was conducted by PSIM software, and the hardware of the DC/DC converter was also implemented. It is necessary to study the fact that the output voltage depends on the duty rate of D, and to compare the output of experimental result with the theory and the simulation.