• Communications of the Korean Mathematical Society
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• v.39 no.2
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• pp.279-302
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• 2024

In this paper, we summarise and present results on involution lengths and commutator lengths of certain linear groups such as special linear groups, projective linear groups, upper triangle matrix groups and Vershik-Kerov groups. Some open problems motivated by these results are also proposed.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.720-722
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• 2000

Single phase series commutator motors is widely used in various home appliances, such as vacuum cleaner, electric mixers, electrical tools, etc. This paper deals with the characteristics of single phase series commutator motors of which parameters varied with stator turns and stack length to find optimal electric and magnetic loading. We try to measure these data through the experiments with several prototype motors. The experimental results show some specific stator turns and stack length with which this motor has the highest efficiency.

• Bulletin of the Korean Mathematical Society
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• v.43 no.4
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• pp.805-812
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• 2006

In this paper we find a suitable bound for the number of commutators which is required to express every element of the derived group of a solvable group satisfying the maximal condition for normal subgroups. The precise formulas for expressing every element of the derived group to the minimal number of commutators are given.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.2
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• pp.97-102
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• 2010

In this paper, an area-efficient FFT processor is proposed for IEEE 802.16e mobile WiMax systems. The proposed scalable FFT processor can support the variable length of 128, 512, 1024 and 2048. By reducing the required number of non-trivial multipliers with mixed-radix (MR) and multi-path delay commutator (MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased without sacrificing system throughput. The proposed FFT processor was designed in hardware description language (HDL) and synthesized to gate-level circuits using 0.18um CMOS standard cell library. With the proposed architecture, the gate count for the processor is 46K and the size of memory is 64Kbits, which are reduced by 16% and 27%, respectively, compared with those of the 4-channel radix-2 MDC (R2MDC) FFT processor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.87-95
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• 2009

In this paper, an area-efficient FFT processor is proposed for MIMO-OFDM based SDR systems. The proposed scalable FFT processor can support the variable length of 64, 128, 512, 1024 and 2048. By reducing the required number of non-trivial multipliers with mixed-radix (MR) and multi-path delay commutator (MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased without sacrificing system throughput The proposed FFT processor was designed in hardware description language (HDL) and synthesized to gate4eve1 circuits using 0.18um CMOS standard cell library. With the proposed architecture, the gate count for the processor is 46K and the size of memory is 64Kbits, which are reduced by 59% and 39%, respectively, compared with those of the 4-channel radix-2 single-path delay feedback (R2SDF) FFT processor. Also, compared with 4-channel radix-2 MDC (R2MDC) FFT processor, it is confirmed that the gate count and memory size are reduced by 16.4% and 26.8, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.621-622
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• 2017

In this paper, a low-complexity FFT processor is proposed for narrow-band interference signal cancellation based array antenna. The proposed FFT pocessor can support the variable length of 64, 128 and 512. By reducing number of non-tirval multipliers with mixed radix-4/2/4/2/4/2 algorithm and flexible multi-path delay commutator(MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased. The proposed FFT processor was designed in Xilinx system generator and Implemented with Xilinx Virtex-7 FPGA. With the proposed architecture, the number of slices for the processor is 11454, and the number of DSP48s is 194.

• Journal of Advanced Navigation Technology
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• v.21 no.6
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• pp.659-665
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• 2017

In this paper, a low complexity fast Fourier transform(FFT) processor is proposed for multiple input multiple output(MIMO) systems. The IEEE 802.11ac standard has been adopted along with the demand for a system capable of high channel capacity and Gbps transmission in order to utilize various multimedia services using a wireless LAN. The proposed scalable FFT processor can support the variable length of 64, 128, 256, and 512 for 8x8 antenna configuration as specified in IEEE 802.11ac standard with MIMO-OFDM scheme. By reducing the required number of non-trivial multipliers with mixed-radix(MR) and multipath delay commutator(MDC) architecture, the complexity of the proposed FFT processor was dramatically decreased. Implementation results show that the proposed FFT processor can reduced the logic gate count by 50%, compared with the radix-2 SDF FFT processor. Also, compared with the 8-channel MR-2/2/2/4/2/4/2 MDC processor and 8-channel MR-2/2/2/8/8 MDC processor, it is shown that the gate count is reduced by 18% and 17% respectively.

• Journal of Applied Reliability
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• v.18 no.3
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• pp.193-200
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• 2018

Purpose: In this study, the life of the motor is investigated by performing the accelerated life test with the brush wear of the industrial cleaner motor as the main failure mode. Methods: The accelerating stress factor of the accelerated life test is a voltage, which can increase the number of revolutions of the motor to accelerate the brush wear due to the friction between the brush and the commutator. Also, the accelerating stress level was determined after determining the maximum allowable level of the voltage through the preliminary test. Results: The motor failure time at each accelerating stress level was predicted by regression analysis with brush wear length as performance degradation data. The main failure mode, which is brush wear, of the motor was reproduced by this test. The shape parameter of the Weibull distribution was confirmed to be the same statistically at all accelerating stress levels by the likelihood ratio test. Conclusion: The life of the motor was investigated by performing the accelerated life test with the brush wear of the industrial cleaner motor as the main failure mode. Through the accelerating test method of the cleaner motor, various life expectancy and life expectancy of the acceleration factor are predicted.