• 제어로봇시스템학회:학술대회논문집
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• 1990.10b
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• pp.1327-1331
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• 1990

A new dual loop controller using color LCD bar graphs with LED back lights has been developed. An optional memory card is used to load or save the controller configuration, which may be a preprogrammed standard package or a user-programmed configuration, in addition to the built-in functions ready for user selection. The bar-graph display is selectable for single-loop or dual-loop use. A high grade of self-tuning functions using a modeling technique is built-in as standard. The controller can accommodate optional plug-in modules for thermocouples, communication, etc. All the options are fully field upgradable.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.10
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• pp.1923-1928
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• 2010

The IEC 61850 protocol proposed for the interoperability between IEDs(intelligent electronic devices) adopts the prioritized switched ethernet as its communication channel because substation bus is utilized to exchange both real-time and non real-time messages. The prioritized switched ethernet uses IEEE 802.1Q/p QoS(Quality of Service) in addition to IEEE 802.3 ethernet to enhance the real-time characteristics. However, IEEE 802.1Q/p QoS has priority-blocking problem that occurs when higher-priority frame transmission request during lower-priority frame transmission. To resolve this problem, this paper proposes P(Preemptive)-Ethernet. P-Ethernet uses the modified IEEE 802.1Q/p frame format and new priority preemption mechanism. This paper also implements P-Ethernet controller using FPGA (Virtex-4) and MicroBlaze processor. From the implementation results, P-Ethernet controller shows a improved latency and jitter of transmission period compare to the normal ethernet controller.

• Journal of Institute of Control, Robotics and Systems
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• v.12 no.8
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• pp.834-841
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• 2006

Recently, many enterprises are installing AMSs(Automated Manufacturing Systems) for their competitive advantages. As the level of automation increases, proper design and validation of control logic is a imperative task for the successful operation of AMSs. However, current discrete event simulation methods mainly focus on the performance evaluation. As a result, they lack the modeling capabilities for the detail logic of automated manufacturing system controller. Proposed in this paper is a method of validation of the controller logic for automated material handling system using an object-oriented design and simulation. Using this method, FA engineers can validate the controller logic easily in earlier stage of system design, so they can reduce the time for correcting the logic errors and enhance the productivity of control program development Generated simulation model can also be used as a communication tool among FA engineers who have different experiences and disciplines.

• Journal of IKEEE
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• v.20 no.3
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• pp.333-336
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• 2016

LIN (local interconnect network) is a standard low-speed serial communication protocol, and it was developed as an efficient sub-bus for automotive electronic modules. In this paper, a LIN controller was implemented in Verilog HDL, based on LIN ver. 2.2A. The implemented LIN controller was verified in FPGA, and it can be supplied as an IP to be integrated into SoC system. Its size is about 2,300 gates when synthesized in 0.18um technology.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.1
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• pp.19-26
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• 1998

In this paper, Simulation result was studied by PID controller in series to the estblised neural networks controller. Neural network model is composed of two layers to evaluate tracking performance improvement. The regular dynamics was also studied for the expected error to be minimized by using Widrow-Hoff delta rule. As a result of the study, We identified that tracking performance improvement was developed more in case of connecting PID than conventional neural network controller and that tracking plant parameter in 251 sample was approached rapidly in case of time varying.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.1
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• pp.1-5
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• 2002

A common way to design a digital control system is to design an analog controller first and discretize it for digital implemention. In this paper, optimal digital controller design is studied within the framework of sampled -data control theory. In particular, multirate discretization of analog controller is considered using an Η$_2$optimality criterion. Solutions are obtained via multirate H2 optimization with a causality constraint due to the multirate structure. In design example, the comparison of the proposed methods is made with the conventional discretization methods, and demonstrate the superiority of the multirate design method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.12
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• pp.2365-2370
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• 2008

In this paper, applications of wavelet neural network controller to position control of nonlinear system are considered. Wavelet neural network is used in the objectives which improve the efficiency of LQR controllers. It is possible to make unstable nonlinear systems stable by using LQR(Linear Quadratic Regulator) technique. And, in order to be adapted to disturbance effectively in this system it uses wavelet neural network controller. Applying this method to the position control of nonlinear system, its usefulness is verified from the results of experiment.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.148-153
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• 2023

A digital controller uses a microprocessor and is a controller implemented as a program. This method has the advantage of being more maintenance-friendly than existing analog controllers. However, it inevitably requires computation time to execute the internal program. Therefore, the digital controller uses a method of controlling the system at a certain cycle by considering this time, and this cycle is very closely related to the performance of the microprocessor used. In other words, in the case of very high performance, this control cycle can be shortened to near real time, but this may result in a disadvantage in terms of cost. In this paper, we propose a method to solve this problem by implementing two processors with slightly lower performance in a control system in a series-parallel structure. For this purpose, we will use a digital distributed control system and implement an experimental system to examine its effectiveness.

• Journal of Power Electronics
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• v.12 no.4
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• pp.623-631
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• 2012

In this paper, a digital controller design procedure is presented for single-phase voltage-doubler boost rectifiers (VDBR). The model derivation of the single-phase VDBR is performed in the s-domain. After that the simplified equivalent z-domain models are derived. These z-domain models are utilized to design the input current and the output dc-link voltage controllers. For the controller design in the z-domain, the traditional K-factor method is modified by considering the nature of the digital controller. The frequency pre-warping and anti-windup techniques are adapted for the controller design. By using the proposed method, the phase margin and the control bandwidth are accurately achieved as required by controller designers in a practical frequency range. The proposed method is applied to a 2.5 kVA single-phase VDBR for Uninterruptible Power Supply (UPS) applications. From the simulation and the experimental results, the effectiveness of the proposed design method has been verified.

• The Transactions of the Korea Information Processing Society
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• v.3 no.5
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• pp.1229-1239
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• 1996

The increase of additional information broadcasting of TV demands a graphic overlay processor. This paper is about the design, implementation and testing of a graphic overlay processor called by KBPS decoder ASSP (Applicatio n Specific Standard Product) which is compliance with Korea Broadcast Programming System. KBPS decoder ASSP consists of embedded 8 bit microprocessor Z80, graphic overlay controller, KBPS schedule decoder, memory controller, priority interrupt controller, MIDI controller, infrared raccoon receiver, async scrial communication controller, timer, bus controller, universal parallel input-output port and serial-parallel interface. The 0.8 micron CMOS Sea of Gate is used to implement the ASSP in amount of about 31,500 gates, and it is running at 14.318MHz.