• 한국정보통신학회논문지
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• 제8권2호
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• pp.365-370
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• 2004

본 논문에서는 복잡계를 이용한 비밀통신 방법을 제시한다. 복잡계 회로는 N-Double Scroll CNN 회로를 이용하였다. 동일한 여러 개의 셀을 가진 N-Double Scroll 회로를 이용하여 복잡계의 송ㆍ수신부를 구성하고 이 복잡계 송ㆍ수신부 사이에 임베딩 동기화 기법을 이용하여 동기화를 이루고, 송신부에서 정보 신호를 복잡계 신호에 합성하여 채널을 통하여 수신부에 송신 한 후 수신부에서 정보 신호와 복잡계 신호를 분리하는 기법을 제시하여 비밀 통신 가능성을 확인하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.465-472
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• 2013

This paper presents a low-complexity triple-error-correcting parallel Bose-Chaudhuri-Hocquenghem (BCH) decoder architecture and its efficient design techniques. A novel modified step-by-step (m-SBS) decoding algorithm, which significantly reduces computational complexity, is proposed for the parallel BCH decoder. In addition, a determinant calculator and a error locator are proposed to reduce hardware complexity. Specifically, a sharing syndrome factor calculator and a self-error detection scheme are proposed. The multi-channel multi-parallel BCH decoder using the proposed m-SBS algorithm and design techniques have considerably less hardware complexity and latency than those using a conventional algorithms. For a 16-channel 4-parallel (1020, 990) BCH decoder over GF($2^{12}$), the proposed design can lead to a reduction in complexity of at least 23 % compared to conventional architecttures.

• 디자인학연구
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• 제14권1호
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• pp.111-118
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• 2001

본 연구의 근본 목적은 사용자의 커뮤니케이션에 대해 복잡성을 사용하는 시각적 요소 수준의 효과를 파악하는 것이다. 실험에서 커뮤니케이션 효율성을 시험해 보기 위해 복잡성을 사용한 여섯 개 수준의 시각적 요소가 네 개의 아이템(그래픽, 동적인 그래픽, 사이즈, 링크)으로 조절되었다. 연구결과, 사용자의 커뮤니케이션은 시각적 요소의 복잡성에 영향을 받았다. 이는 복잡하고 간단한 수준의 시각적 요소보다 적절한 수준의 시각적 요소로 디자인된 웹사이트가 더 선호된다는 것을 입증하고 있다.

• 정보보호학회논문지
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• 제12권3호
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• pp.95-102
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• 2002

Interactive hashing은 Naor, Ostrovsky, Venkatesan, Yung〔1〕에 의해 소개된 프로토콜로 주어진 스트링 크기 t비트에 대해 t-1번의 라운드 복잡도(round complexity)와 $t^2$-1 비트의 전송 복잡도(communication complexity)를 가진다. 본 논문은 t를 나누는 m에 대해서 t/m-1번의 라운드 복잡도와 $t^2$/m - m 비트의 전송 복잡도를 갖는 NOVY 프로토콜보다 효율적으로 확장된 Interactive hashing 프로토콜을 제안하고 그 안전성을 증명한다.

• 한국통신학회논문지
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• 제18권5호
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• pp.695-707
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• 1993

Marked Petri Net(MPN) 모델은 최대 병행 활성화 랑데부 수에 따른 통신 복잡도를 분석할 수 있게 해준다. 그러나 이 모델은 시간과 확률 속성(Time and Probability characteristics)을 명시할 수 없음으로 통신 복잡도의 새로운 개념인 실행 시간 복잡도를 분석할 수 없다. 본 논문에서는 이러한 실행 시간 복잡도를 효율적으로 분석하기 위해 MPN에 새로운 제약 조건인 net 절감 법칙, 실행 시간, 그리고 확률 조건을 도입한 Ada Tasking Structure Nets(ATSN)을 제안한다. 끝으로 ATSN 모델을 이용하여 통신 복잡도의 분석 효과를 보인다.

• Journal of Electrical Engineering and Technology
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• 제11권4호
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• pp.1020-1026
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• 2016

Motion estimation (ME) algorithms supporting quarter-pixel accuracy have been recently introduced to retain detailed motion information for high quality of video in the state-of-the-art video compression standard of H.264/AVC. Conventional sub-pixel ME algorithms in the spatial domain are faced with a common problem of computational complexity because of embedded interpolation schemes. This paper proposes a low-complexity sub-pixel motion estimation algorithm in the transform domain utilizing shifting matrix. Simulations are performed to compare the performances of spatial-domain ME algorithms and transform-domain ME algorithms in terms of peak signal-to-noise ratio (PSNR) and the number of bits per frame. Simulation results confirm that the transform-domain approach not only improves the video quality and the compression efficiency, but also remarkably alleviates the computational complexity, compared to the spatial-domain approach.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권3호
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• pp.427-435
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• 2015

This paper presents a high-throughput low-complexity decoder architecture and design technique to implement successive-cancellation (SC) polar decoding. A novel merged processing element with a one's complement scheme, a main frame with optimal internal word length, and optimized feedback part architecture are proposed. Generally, a polar decoder uses a two's complement scheme in merged processing elements, in which a conversion between two's complement and sign-magnitude requires an adder. However, the novel merged processing elements do not require an adder. Moreover, in order to reduce hardware complexity, optimized main frame and feedback part approaches are also presented. A (1024, 512) SC polar decoder was designed and implemented using 40-nm CMOS standard cell technology. Synthesis results show that the proposed SC polar decoder can lead to a 13% reduction in hardware complexity and a higher clock speed compared to conventional decoders.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.533-534
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• 2006

This paper presents the architecture design of a high-speed, low-complexity 128-point radix-$2^4$ FFT processor for ultra-wideband (UWB) systems. The proposed high-speed, low-complexity FFT architecture can provide a higher throughput rate and low hardware complexity by using 2-parallel data-path scheme and single-path delay-feedback (SDF) structure. This paper presents the key ideas applied to the design of high-speed, low-complexity FFT processor, especially that for achieving high throughput rate and reducing hardware complexity. The proposed FFT processor has been designed and implemented with the 0.18-m CMOS technology in a supply voltage of 1.8 V. The throughput rate of proposed FFT processor is up to 1 Gsample/s while it requires much smaller hardware complexity.

• Journal of Positioning, Navigation, and Timing
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• 제11권2호
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• pp.91-98
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• 2022

In the next generation wireless communication system, the beamforming technique based on a massive antenna is one of core technologies for transmitting and receiving huge amounts of data, efficiently and accurately. For highly performed and highly reliable beamforming, it is required to accurately estimate the Angle of Arrival (AOA) for the desired signal incident to an antenna. Employing the massive antenna with a large number of elements, although the accuracy of the AOA estimation is enhanced, its computational complexity is dramatically increased so much that real-time communication is difficult. In order to improve this problem, AOA estimation algorithms based on the massive antenna with the low computational complexity have been actively studied. In this paper, we compute and analyze the computational complexity of the cascade AOA estimation algorithm based on the Flexible Massive Concentric Circular Array (FMCCA). In addition, its computational complexity is compared to conventional AOA estimation techniques such as the Multiple Signal Classification (MUSIC) algorithm with the high resolution and the Only Beamspace MUSIC (OBM) algorithm.

• ETRI Journal
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• 제35권3호
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• pp.371-377
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• 2013

An effective signal detection algorithm with low complexity is presented for multiple-input multiple-output orthogonal frequency division multiplexing systems. The proposed technique, QR-MLD, combines the conventional maximum likelihood detection (MLD) algorithm and the QR algorithm, resulting in much lower complexity compared to MLD. The proposed technique is compared with a similar algorithm, showing that the complexity of the proposed technique with T=1 is a 95% improvement over that of MLD, at the expense of about a 2-dB signal-to-noise-ratio (SNR) degradation for a bit error rate (BER) of $10^{-3}$. Additionally, with T=2, the proposed technique reduces the complexity by 73% for multiplications and 80% for additions and enhances the SNR performance about 1 dB for a BER of $10^{-3}$.