• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.365-370
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• 2004

In this paper, complexity secure communication was presented. The complexity circuit is used to State-Controlled Cellular Neural Network(SC-CNN). We make a complexity circuit using SC-CNN with the N-double scroll. A complexity circuit is created by applying identical n-double scrolls with coupled method, to each cell. complexity synchronization was achieved using drive response synchronization between the transmitter and receiver about each state in the SC-CNN. From the result of the recovery signal through the demodulation method in the receiver. We shown that recovery quality in the receiver is the similar to other secure communication methods.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.465-472
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• 2013

This paper presents a low-complexity triple-error-correcting parallel Bose-Chaudhuri-Hocquenghem (BCH) decoder architecture and its efficient design techniques. A novel modified step-by-step (m-SBS) decoding algorithm, which significantly reduces computational complexity, is proposed for the parallel BCH decoder. In addition, a determinant calculator and a error locator are proposed to reduce hardware complexity. Specifically, a sharing syndrome factor calculator and a self-error detection scheme are proposed. The multi-channel multi-parallel BCH decoder using the proposed m-SBS algorithm and design techniques have considerably less hardware complexity and latency than those using a conventional algorithms. For a 16-channel 4-parallel (1020, 990) BCH decoder over GF($2^{12}$), the proposed design can lead to a reduction in complexity of at least 23 % compared to conventional architecttures.

• Archives of design research
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• v.14 no.1
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• pp.111-118
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• 2001

The primary purpose of this research is to identify effects of the complexity levels of visual factors on user's communication in the web-sites. In this study, six complexity levels of visual factors were manipulated with four items(graphics, moving graphics, size and links) to test communication effects. As a result, user's communication was influenced by the complexity of illustration. This result shows that web sites with moderate levels of illustration complexity are more preferred than with complex or simple levels of visual complexity.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.3
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• pp.95-102
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• 2002

Interactive hashing is a protocol introduced by Naor, Ostrovsk Venkatesan, $Yung^{[1]}$ with t-1 round complexity and $t^2$ - 1 bits communication complexity for given t bits string. In this paper, we propose more efficiently extended interactive hashing protocol with t/m- 1 round complexity and $t^2$/m - m bits communication complexity than NOVY protocol when m is a divisor of t, and prove the security of this.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.5
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• pp.695-707
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• 1993

Marked Petri Net(MPN) is used to analyze communication complexity with respect to the maximum number of concurrently active rendezvous. But, because it cannot represent timed & probability characteristics explicitly, it is not used to analyze the new execution time of complexity with respect to the communication. Thus to effectively analyze that execution time complexity, we propose Ada Tasking Structure Nets (ATSN) introduced restrictive conditions : net reduction rules, execution time, and probability. Finally, we show the powers of analyze of communication complexity with ATSN.

• Journal of Electrical Engineering and Technology
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• v.11 no.4
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• pp.1020-1026
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• 2016

Motion estimation (ME) algorithms supporting quarter-pixel accuracy have been recently introduced to retain detailed motion information for high quality of video in the state-of-the-art video compression standard of H.264/AVC. Conventional sub-pixel ME algorithms in the spatial domain are faced with a common problem of computational complexity because of embedded interpolation schemes. This paper proposes a low-complexity sub-pixel motion estimation algorithm in the transform domain utilizing shifting matrix. Simulations are performed to compare the performances of spatial-domain ME algorithms and transform-domain ME algorithms in terms of peak signal-to-noise ratio (PSNR) and the number of bits per frame. Simulation results confirm that the transform-domain approach not only improves the video quality and the compression efficiency, but also remarkably alleviates the computational complexity, compared to the spatial-domain approach.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.427-435
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• 2015

This paper presents a high-throughput low-complexity decoder architecture and design technique to implement successive-cancellation (SC) polar decoding. A novel merged processing element with a one's complement scheme, a main frame with optimal internal word length, and optimized feedback part architecture are proposed. Generally, a polar decoder uses a two's complement scheme in merged processing elements, in which a conversion between two's complement and sign-magnitude requires an adder. However, the novel merged processing elements do not require an adder. Moreover, in order to reduce hardware complexity, optimized main frame and feedback part approaches are also presented. A (1024, 512) SC polar decoder was designed and implemented using 40-nm CMOS standard cell technology. Synthesis results show that the proposed SC polar decoder can lead to a 13% reduction in hardware complexity and a higher clock speed compared to conventional decoders.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.533-534
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• 2006

This paper presents the architecture design of a high-speed, low-complexity 128-point radix-$2^4$ FFT processor for ultra-wideband (UWB) systems. The proposed high-speed, low-complexity FFT architecture can provide a higher throughput rate and low hardware complexity by using 2-parallel data-path scheme and single-path delay-feedback (SDF) structure. This paper presents the key ideas applied to the design of high-speed, low-complexity FFT processor, especially that for achieving high throughput rate and reducing hardware complexity. The proposed FFT processor has been designed and implemented with the 0.18-m CMOS technology in a supply voltage of 1.8 V. The throughput rate of proposed FFT processor is up to 1 Gsample/s while it requires much smaller hardware complexity.

• Journal of Positioning, Navigation, and Timing
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• v.11 no.2
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• pp.91-98
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• 2022

In the next generation wireless communication system, the beamforming technique based on a massive antenna is one of core technologies for transmitting and receiving huge amounts of data, efficiently and accurately. For highly performed and highly reliable beamforming, it is required to accurately estimate the Angle of Arrival (AOA) for the desired signal incident to an antenna. Employing the massive antenna with a large number of elements, although the accuracy of the AOA estimation is enhanced, its computational complexity is dramatically increased so much that real-time communication is difficult. In order to improve this problem, AOA estimation algorithms based on the massive antenna with the low computational complexity have been actively studied. In this paper, we compute and analyze the computational complexity of the cascade AOA estimation algorithm based on the Flexible Massive Concentric Circular Array (FMCCA). In addition, its computational complexity is compared to conventional AOA estimation techniques such as the Multiple Signal Classification (MUSIC) algorithm with the high resolution and the Only Beamspace MUSIC (OBM) algorithm.

• ETRI Journal
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• v.35 no.3
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• pp.371-377
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• 2013

An effective signal detection algorithm with low complexity is presented for multiple-input multiple-output orthogonal frequency division multiplexing systems. The proposed technique, QR-MLD, combines the conventional maximum likelihood detection (MLD) algorithm and the QR algorithm, resulting in much lower complexity compared to MLD. The proposed technique is compared with a similar algorithm, showing that the complexity of the proposed technique with T=1 is a 95% improvement over that of MLD, at the expense of about a 2-dB signal-to-noise-ratio (SNR) degradation for a bit error rate (BER) of $10^{-3}$. Additionally, with T=2, the proposed technique reduces the complexity by 73% for multiplications and 80% for additions and enhances the SNR performance about 1 dB for a BER of $10^{-3}$.