• ETRI Journal
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• v.27 no.1
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• pp.81-88
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• 2005

In this paper, interface circuits that are suitable for point-to-point interconnection with an over 1 Gbps data rate per pin are proposed. To achieve a successful data transfer rate of multi-gigabits per-second between two chips with a point-to-point interconnection, the input receiver uses an on-chip parallel terminator of the pass gate style, while the output driver uses the pullup and pulldown transistors of the diode-connected style. In addition, the novel dynamic voltage level converter (DVLC) has solved such problems as the access time increase and valid data window reduction. These schemes were adopted on a 64 Mb DDR SRAM with a 1.5 Gbps data rate per pin and fabricated using a 0.10 ${\mu}m$ dual gate oxide CMOS technology.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.1967-1977
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• 2014

In this paper, for the development of a safe and reliable DC home appliance suitable for DC home power supply system, we classified a number of inherent problems with help of the comparative analysis of existing AC and new DC home appliance. Several new technical problems of DC home appliances are mainly linked to the DC transient state. Among them, this paper concentrates on start-up inrush current problem, uni-polarity problem, and heavy DC load control problem. And to address these problems, we herein present an implementation of robust safety circuits for DC home appliances. Specifically, we investigate several multi-circuit countermeasures and select the best among them through comparative evaluation, based on theoretical, simulational, and experimental results.

• Journal of information and communication convergence engineering
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• v.1 no.4
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• pp.177-182
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• 2003

Conventional multilayer feedforward artificial neural networks are very effective in dealing with spatial problems. To deal with problems with time dependency, some kinds of memory have to be built in the processing algorithm. In this paper we show how the newly proposed Serial Input Neuron (SIN) convolutional decoders can be derived. As an example, we derive the SIN decoder for rate code with constraint length 3. The SIN is tested in Gaussian channel and the results are compared to the results of the optimal Viterbi decoder. A SIN approach to decode convolutional codes is presented. No supervision is required. The decoder lends itself to pleasing implementations in hardware and processing codes with high speed in a time. However, the speed of the current circuits may set limits to the codes used. With increasing speeds of the circuits in the future, the proposed technique may become a tempting choice for decoding convolutional coding with long constraint lengths.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1192-1195
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• 2002

In this paper, we propose Low-Power Receiver circuits for a wireless communication system using ASK signal. Their structures are suitable for low supply current. The proposed circuits are designed and simulated by Spectre using 0.8m CMOS process parameters, and operate with supply current below 1.5${\mu}\textrm{A}$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.12
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• pp.54-62
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• 2003

A systematic synthesis process is described lot the simulation of current-controllable inductors using operational transconductance amplifiers (OTAs). The process is used to obtain three circuits; two are believed It) be novel. The process is also applied to design current-controllable frequency-dependent negative resistances (FDNRs). Operation principles of designed circuits are presented and experimental results are used to verify theoretical predictions. The results show close agreement between predicted behavior and experimental performance. The application of a FDNR to a current-controllable band-pass filter is also presented.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.29-32
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• 2000

In this paper, an analytical model for I-V characteristics of a HEMTs is Proposed. The developed model takes into account the temperature dependence of drain current. In high-speed ICs for optical communication systems and mobile communication systems, temperature variation affects performance; for example the gain, efficiency in analog circuits and the delay time, power consumption and noise mrgin in digital circuits. To design such a circuit taking into account the temperature dependence of the current-voltage characteristic is indispensible. This model based on the analytical relation between surface carrier density and Fermi potential including temperature dependent coefficients.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.2
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• pp.351-356
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• 2022

The parity function can be implemented with XOR (exclusive-OR) and XNOR (exclusive NOR) circuit. In this paper we propose a high performance XOR-XNOR circuit. The proposed circuitreduced the internal load capacitance on critical path and implemented with 8 transistors. The circuit produces a perfect output signals for all input combinations. Compared with the previous circuits, the proposed circuit presents the improved characteristics in average propagation delay time, power dissipation, power-delay product (PDP), and energy-delay-product (EDP). The proposed circuits are implemented with standard CMOS 0.18um technology. Computer simulations using SPICE show that the proposed circuit realizes the expected logic functions and achieves a reasonable performance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.322-330
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• 2014

New effective techniques to repair "small" design errors in integrated circuits are presented. As semiconductor chip complexity increases and the design period becomes tight, errors frequently remain in a fabricated chip making revisions required. Full mask revision significantly increases the cost and time-to-market. However, since many "small" errors can be repaired by modifying several connections among the circuit blocks and spare cells, errors can frequently be repaired by revising metal layers. Metal only revision takes significantly less time and involves less cost when compared to full mask revision, since mask revision costs multi-million dollars while metal revision costs tens of thousand dollars. In our research, new techniques are developed to further reduce the number of metal layers to be revised. Specifically, we partition the circuit blocks with higher error probabilities and extend the terminals of the signals crossing the partition boundaries to the preselected metal repair layers. Our partitioning and pin extension to repair layers can significantly improve the repairability by revising only the metal repair layers. Since pin extension may increase delay slightly, this method can be used for non-timing-critical parts of circuits. Experimental results by using academia and industrial circuits show that the revision of the two metal layers can repair many "small" errors at low-cost and with short revision time. On the average, when 11.64% of the spare cell area and 24.72% of the extended pins are added to the original circuits, 83.74% of the single errors (and 72.22% of the double errors) can be corrected by using two metal revision. We also suggest methods to use our repair techniques with normal commercial vender tools.

• Electronics and Telecommunications Trends
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• v.36 no.3
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• pp.53-64
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• 2021

As the 5G service market is expected to grow rapidly, the development of high-power, high-efficiency power amplifiers for the 5G communication infrastructure is indispensable. Gallium nitride (GaN) is attracting great interest as a key device in power devices and integrated circuits due to its wide bandgap, high carrier concentration, high electron mobility, and high-power saturation characteristics. In this study, we investigate the technology trends of Ka-band GaN radio frequency (RF) power devices and integrated circuits for operation in the millimeter-wave band of recent 5G mobile communication services. We review the characteristics of GaN RF high electron mobility transistor (HEMT) devices to implement power amplifiers operating at frequencies around 28 GHz and compare the technology of foreign companies with the device characteristics currently developed by the Electronics and Telecommunication Research Institute (ETRI). In addition, the characteristics of Ka-band GaN monolithic microwave integrated circuit (MMIC) power amplifiers manufactured using various GaN HEMT device technologies are reviewed by comparing characteristics such as frequency band, output power, and output power density of integrated circuits. In addition, by comparing the performance of the power amplifier developed by ETRI, the current status and future direction of domestic GaN power devices and integrated circuit technology will be discussed.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.519-522
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• 2002

An active phased array antenna consists of many channels. Each channel has a different initial phase shift and gain because of the inequality in the active circuits themselves, interface between radiators and active circuits, and beam-forming circuits and other antenna system configurations. This raises an inherent problem in active phased array antennas. To compensate for this problem the initial phase and gain of each channel should be calibrated. This paper presents an efficient calibration method for an initial phase variation of each channel in active phased array antennas. We tested our method in an active phased array antenna, and obtained good results in the radiation pattern and beam direction of antenna.