• Journal of information and communication convergence engineering
• /
• v.6 no.4
• /
• pp.383-390
• /
• 2008

Clock skew modeling is important in the performance evaluation and prediction of clock distribution network and it is one of the major constraints for high-speed operation of synchronous integrated circuits. In clock routing synthesis, it is necessary to reduce the clock skew under the specified skew bound, while minimizing the cost such as total wire length and delay. In this paper, a new efficient bounded clock skew routing method is described, which generalizes the well-known bounded skew tree method by allowing loops, i.e., link-edges can be inserted to a clock tree when they are beneficial to reduce the clock skew and/or the wire length. Furthermore, routing topology construction and wire sizing is used to reduce clock delay.

• Proceedings of the KIEE Conference
• /
• 2005.07a
• /
• pp.102-104
• /
• 2005

This paper describes the model of the distribution grid for the broadband power line communication based on lumped-element circuits. In addition, this paper discusses various configurations of the MV distribution network in PLC. The distribution grid is not designed for communication so that it involves unfriendly conditions for PLC. The characterization of the MV distribution grid for PLC should be determined such as noise, attenuation, and mismatched impedance. For theses reasons, the PLC networks is described in using the scattering parameters. Finally, the n-port network is explained.

• Journal of the Optical Society of Korea
• /
• v.18 no.6
• /
• pp.639-645
• /
• 2014

In this paper, the scheme of a single module for simultaneous operation of all-optical computing circuits, namely half adder and half subtractor, are realized using semiconductor optical amplifier (SOA) based logic gates. Optical XOR gate by employing a SOA based Mach-Zehnder interferometer (MZI) configuration is used to get the sum and difference outputs. A carry signal is generated using a SOA-four wave mixing (FWM) based AND gate, whereas, the borrow is generated by employing the SOA-cross gain modulation (XGM) effect. The obtained results confirm the feasibility of our configuration by proving the good level of quality factor i.e. ~5.5, 9.95 and 12.51 for sum/difference, carry and borrow, respectively at 0 dBm of input power.

• Journal of Sensor Science and Technology
• /
• v.25 no.3
• /
• pp.189-195
• /
• 2016

In this paper, we newly introduce a visible light communication (VLC) repeater using the LED array in an LED lamp. The LED array is used for a light source in the repeater, which radiates light both for illumination and data transmission. A VLC repeater is made by adding some electronic circuits to the LED array including a photodetector, a demodulator, and a modulator. The repeater is installed on the ceiling of a room like a conventional LED lamp, receives the VLC signal from an arbitrary transmitter, recovers data, and radiates the signal to wide area in the room. We used a carrier frequency of 100 kHz for the uplink from a transmitter to the repeater, and 500 kHz for the downlink from the repeater to a receiver. The repeater is useful for increasing the transmission path to wide area over the obstacles that may exist between VLC transmitters and receivers.

• IEIE Transactions on Smart Processing and Computing
• /
• v.3 no.6
• /
• pp.410-415
• /
• 2014

This paper presents a new rectifier with a bootstrapping technique to reduce the effective drop voltage. An all-digital delay locked loop (ADDLL) circuit was also applied to prevent the reverse leakage current. The proposed rectifier uses NMOS diode connected instead of PMOS to reduce the design size and improve the frequency respond. All the sub-circuits of ADDLL were designed with low power consumption to reduce the total power of the rectifier. The rectifier was implemented in CMOS $0.35{\mu}m$ technology. The peak power conversion efficiency was 76 % at an input frequency of 6.78MHz and a power level of 5W.

• Proceedings of the KIEE Conference
• /
• 2005.11a
• /
• pp.172-175
• /
• 2005

a-Si TFT는 TFT-LCD의 화소 스위칭(swiching) 소자로 폭넓게 이용되고 있다. 현재는 a-Si을 이용하여 gate drive IC를 기판에 집적하는 기술이 연구, 적용되고 있는데 이때 가장 큰 제약은 문턱 전압의 이동이다. 펄스(pulse)형태로 인가되는 gate 전압에 의한 문턱 전압 이동은 a-Si:H gate에 인가되는 펄스의 크기, duty cycle, drain pulse의 크기 및 동작 온도에 기인하며 실험결과를 통해 입증된다. 초기의 DC Stress 측정 Data를 이용하여 문턱전압이동을 모델링/시뮬레이션한 결과 a-Si:H gate 회로설계 및 펄스 조건에 따라 stress시간에 따른 gate의 출력 파형 예측이 가능하고 상온에서 Von=21V를 인가한 결과, 약 4년후에서 시프트레지스터 출력 파형이 열화되기 시작한다.

• Journal of Electrical Engineering and Technology
• /
• v.8 no.1
• /
• pp.11-19
• /
• 2013

Very Fast Transients (VFT) originate mainly from disconnector switching operations in Gas Insulated Substations (GIS). In order to determine the rate-of-rise of Very Fast Transient Overvoltage (VFTO) in a 550 kV GIS, simulations are carried out using EMTP-RV. Each component of the GIS is modeled by distributed line model and lumped model based on equivalent circuits. The various switching conditions according to closing point-on-wave and trapped charge are simulated, and the results are analyzed. Also, the analysis of travelling wave using a lattice diagram is conducted to verify the simulation results.

• Proceedings of the KIEE Conference
• /
• 1997.07b
• /
• pp.530-532
• /
• 1997

In this paper, a transmitter and a receiver using two identical Chua's circuits are proposed and a wire secure communications are investigated. A secure communication method in which the desired information signal is synthesized with the chaos signal created by the Chua's circuit is proposed and information signal is demodulated also using the Chua's circuit. The proposed method is synthesizing the desired information with the chaos circuit by adding the information signal to the chaos signal in the wire transmission system. After transmitting the synthesized signal through the wire transmission system, it is confirmed the feasibility of the secure communication from result of demodulated signals and recovered wire tapped signals.

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.485-486
• /
• 2006

This paper proposes a novel low-cost CMOS temperature sensor for controlling the self-refresh period of a mobile DRAM. In this temperature sensor, ring oscillators composed of cascaded inverter stages are used to obtain the temperature of the chip. This method is highly area-efficient, simple and easy for IC implementation as compared to traditional temperature sensors based on analog bandgap reference circuits. The proposed CMOS temperature sensor was fabricated with 80 nm 3-metal DRAM process. It occupies a silicon area of only about less than $0.02\;mm^2$ at $10^{\circ}C$ resolution with under 5uW power consumption at 1 sample/s processing rate. This area is about 33% of conventional temperature sensor in mobile DRAM.

• Proceedings of the KIEE Conference
• /
• 2003.07d
• /
• pp.2158-2160
• /
• 2003

본 논문에서는 동일동기화(Identical Synchronization)과 일반동기화(General Synchronization)를 이용한 하이퍼카오스 시스템을 구성하고 검증하였다. 단일 카오스 모듈을 이용한 통신은 많은 보안의 취약점을 가진 것으로 알려져 있다. 이에 이런 취약점을 보안하기 위해 여러 방법들이 도입되었다. 본 논문은 두 개의 2-double scroll Chua 회로와 두 개의 2-double scroll Chua 오실레이터를 이용하여 하이퍼카오스 회로의 송수 신단을 구성하고 동기화를 이룬 후 송신단에서 정보신호를 실어 채널을 통해 보내어 수신단에서 이를 복조하는 방법을 제안하였다.