• Title/Summary/Keyword: common source line(CSL)

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Investigation for Multi-bit per Cell on the CSL-NOR Type SONOS Flash Memories (CSL-NOR형 SONOS 플래시 메모리의 멀티비트 적용에 관한 연구)

  • Kim Joo-Yeon;An Ho-Myoung;Lee Myung-Shik;Kim Byung-Cheul;Seo Kwang-Yell
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.18 no.3
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    • pp.193-198
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    • 2005
  • NOR type flash 32 ${\times}$ 32 way are fabricated by using the typical 0.35 ${\mu}{\textrm}{m}$ CMOS process. The structure of array is the NOR type with common source line. In this paper, optimized program and erase voltage conditions are presented to realize multi-bit per cell at the CSL-NOR array. These are considered selectivity of selected bit and disturbances of unselected bits. Retention characteristics of locally trapped-charges in the nitride layer are investigated. The lateral diffusion and vertical detrapping to the tunneling oxide of locally trapped charges as a function of retention time are investigated by using the charge pumping method. The results are directly shown by change of the trapped-charges quantities.

Realization of Two-bit Operation by Bulk-biased Programming Technique in SONOS NOR Array with Common Source Lines

  • An, Ho-Myoung;Seo, Kwang-Yell;Kim, Joo-Yeon;Kim, Byung-Cheul
    • Transactions on Electrical and Electronic Materials
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    • v.7 no.4
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    • pp.180-183
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    • 2006
  • We report for the first time two-bit operational characteristics of a high-density NOR-type polysilicon-oxide-nitride-oxide-silicon (SONOS) array with common source line (CSL). An undesired disturbance, especially drain disturbance, in the NOR array with CSL comes from the two-bit-per-cell operation. To solve this problem, we propose an efficient bulk-biased programming technique. In this technique, a bulk bias is additionally applied to the substrate of memory cell for decreasing the electric field between nitride layer and drain region. The proposed programming technique shows free of drain disturbance characteristics. As a result, we have accomplished reliable two-bit SONOS array by employing the proposed programming technique.

A investigation for Local Trapped Charge Distribution and Multi-bit Operation of CSL-NOR type SONOS Flash Memory (CSL-NOR형 SONOS 플래시 메모리의 Multi-bit 적용과 국소 트랩 전하 분포 조사)

  • Kim, Joo-Yeon;An, Ho-Myoung;Han, Tae-Hyeon;Kim, Byung-Cheul;Seo, Kwang-Yell
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2004.07a
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    • pp.37-40
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    • 2004
  • SONOS를 이용한 전하트랩형 플래시 메모리를 통상의 0.35um CMOS 공정을 이용하여 제작하였으며 그 구조는 소스를 공통(CSL. Common Source Line)으로 사용하는 NOR형으로 하였다. 기존의 공정을 그대로 이용하면서 멀티 비트 동작을 통한 실질적 집적도 향상을 얻을 수 있다면 그 의미가 크다고 하겠다. 따라서 본 연구에서는CSL-NOR형 플래시 구조에서 멀티 비트을 구현하기위한 최적의 프로그램/소거/읽기 전압 조건을 구하여 국소적으로 트랩된 전하의 분포를 전하펌핑 방법을 이용하여 조사하였다. 또한 이 방법을 이용하여 멀티 비트 동작 시 문제점으로 제시된 전하의 측면확산을 측정하였다.

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The Write Characteristics of SONOS NOR-Type Flash Memory with Common Source Line (공통 소스라인을 갖는 SONOS NOR 플래시 메모리의 쓰기 특성)

  • An, Ho-Myoung;Han, Tae-Hyeon;Kim, Joo-Yeon;Kim, Byung-Cheul;Kim, Tae-Geun;Seo, Kwang-Yell
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.11a
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    • pp.35-38
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    • 2002
  • In this paper, the characteristics of channel hot electron (CHE) injection for the write operation in a NOR-type SONOS flash memory with common source line were investigated. The thicknesses of he tunnel oxide, the memory nitride, and the blocking oxide layers for the gate insulator of the fabricated SONOS devices were $34{\AA}$, $73{\AA}$, and $34{\AA}$, respectively. The SONOS devices compared to floating gate devices have many advantages, which are a simpler cell structure, compatibility with conventional logic CMOS process and a superior scalability. For these reasons, the introduction of SONOS device has stimulated. In the conventional SONOS devices, Modified Folwer-Nordheim (MFN) tunneling and CHE injection for writing require high voltages, which are typically in the range of 9 V to 15 V. However CHE injection in our devices was achieved with the single power supply of 5 V. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve were investigated. The memory window of about 3.2 V and the write speed of $100{\mu}s$ were obtained. Also, the disturbance and drain turn-on leakage during CHE injection were not affected in the SONOS array. These results show that CHE injection can be achieved with a low voltage and single power supply, and applied for the high speed program of the SONOS memory devices.

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