• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2369-2379
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• 2013

A CMOS x-ray line scan sensor which is used in both medical imaging and non-destructive diagnosis is designed. It has a pixel array of 512 columns ${\times}$ 4 rows and a built-in DC-DC converter. The pixel circuit is newly proposed to have three binning modes such as no binning, $2{\times}2$ binning, and $4{\times}4$ binning in order to select one of pixel sizes of $100{\mu}m$, $200{\mu}m$, and $400{\mu}m$. It is designed to output a fully differential image signal which is insensitive to power supply and input common mode noises. The layout size of the designed line scan sensor with a $0.18{\mu}m$ x-ray CMOS image sensor process is $51,304{\mu}m{\times}5,945{\mu}m$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.1
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• pp.117-122
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• 2016

In this paper, we propose 24-GHz CMOS radio frequency (RF) power amplifier for short-range automotive collision avoidance radars. This circuit contains common source stage with inter-stages conjugate matching circuit as a class-A mode amplifier. The proposed circuit is designed using TSMC $0.13-{\mu}m$ mixed signal/RF CMOS process ($f_T/f_{MAX}=120/140GHz$). It operates at the supply voltage of 2V, and it is designed to have high power gain, low insertion loss and low noise figure in the low supply voltage. To reduce total chip area, the circuit used transmission lines instead of the bulky real inductor. The designed CMOS power amplifier showed the smallest chip size of $0.1mm^2$, the lowest power consumption of 40mW, the highest power gain of 26.5dB, the highest saturated output power of 19.2dBm and the highest maximum power-added efficiency of 17.2% as compared to recently reported results.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.4
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• pp.1903-1907
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• 2013

Heart condition should be observed for long periods of time because it does not appear abnormal all the time. However, there are many difficulties checking our health for a long time due to its size, operation of equipment, and cost. To solve these problems, an electrocardiograms(ECG), specially interfacing three gel-less metal electrodes for low cost portable applications, is designed and implemented. Gel-less metal electrodes are used for ECG monitoring system instead of gel-type electrodes that can cause skin rashes and itching problem. The whole ECG system consists of two parts-analog and digital circuits. The analog measurement circuit that has a 18*25mm size is made up of op-amps maintaining a sufficiently high common-mode noise rejection and passive elements of SMD type. Analog heart signal is converted to digital stream suitable for display on a TFT-LCD by an 8-bit microcontroller. The size of the completed ECG system is 25*80*50mm and its weighing is about 150g, which is small enough to be easily used. Therefore, the implemented ECG system can be used as a portable one.

• ETRI Journal
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• v.38 no.5
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• pp.981-987
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• 2016

We present a cost-effective dual polarization quadrature phase-shift coherent receiver module using a silica planar lightwave circuit (PLC) hybrid assembly. Two polarization beam splitters and two $90^{\circ}$ optical hybrids are monolithically integrated in one silica PLC chip with an index contrast of $2%-{\Delta}$. Two four-channel spot-size converter integrated waveguide-photodetector (PD) arrays are bonded on PD carriers for transverse-electric/transverse-magnetic polarization, and butt-coupled to a polished facet of the PLC using a simple chip-to-chip bonding method. Instead of a ceramic sub-mount, a low-cost printed circuit board is applied in the module. A stepped CuW block is used to dissipate the heat generated from trans-impedance amplifiers and to vertically align RF transmission lines. The fabricated coherent receiver shows a 3-dB bandwidth of 26 GHz and a common mode rejection ratio of 16 dB at 22 GHz for a local oscillator optical input. A bit error rate of $8.3{\times}10^{-11}$ is achieved at a 112-Gbps back-to-back transmission with off-line digital signal processing.

• Journal of the Korean Society for Nondestructive Testing
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• v.21 no.1
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• pp.39-45
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• 2001

Fourier transform has been one of the most common tools to study the frequency characteristics of signals. With the Fourier transform alone, however, it is difficult to tell whether signal's frequency contents evolve in time or not. Except for a few special cases, the frequency contents of most signals encountered in the real world change with time. Time-frequency analysis methods are developed recently to overcome the drawbacks of Fourier transform, which can represent the information of signals in time and frequency at the same time. In this study, damage process of a cross-ply carbon fiber reinforced plastic (CFRP) under monotonic tensile loading was characterized by acoustic emission. Different kinds of CFRP specimens were used to determine the characteristics of AE signals. Time-frequency analysis methods were employed for the analysis of fracture mechanisms in CFRP such as mix cracking, debonding, fiber fracture and delamination.

• Journal of Broadcast Engineering
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• v.24 no.6
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• pp.1035-1052
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• 2019

Recently, as the demand for immersive videos increases, efficient video processing techniques for omnidirectional immersive video is actively developed by MPEG-I. While the omnidirectional video provides a larger degree of freedom for a free viewpoint, the size of the video increases significantly. Furthermore, in order to compress 6 degree-of-freedom (6 DoF) videos that support motion parallax, it is required to develop a codec to yield better coding efficiency. In this paper, we develop a 6 DoF codec using Versatile Video Coding (VVC) as the next generation video coding standard. To the authors' best knowledge, this is the first VVC-based 6 DoF video codec toward the future ISO/IEC 23090 Part 7 (Metadata for Immersive Media (Video)) MPEG-I standardization. The experiments were conducted on the seven test video sequences specified in Common Test Condition (CTC) in two operation modes of TMIV (Test Model for Immersive Media) software. It is demonstrated that the proposed codec improves coding performance around 33.8% BD-rate reduction in the MIV (Metadata for Immersive Video) mode and 30.2% BD-rate reduction in the MIV view mode as compared to the state-of-the-art TMIV reference software. We also show the performance comparisons using Immersive Video PSNR (IV-PSNR) and Mean Structural Similarity (MSSIM).

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.3
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• pp.184-196
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for precision measurement of current flowing through a secondary cell battery in a battery management system (BMS). The proposed modulator implements two switched capacitor integrators and a single-bit comparator with peripheral circuits such as a non-overlapping clock generator and a bias circuit. The proposed structure is designed to be applied to low-side current sensing method with low common mode input voltage. Using the low-side current measurement method has the advantage of reducing the burden on the circuit design. In addition, the ±30mV input voltage is resolved by the ADC with 15-bit resolution, eliminating the need for an additional programmable gain amplifier (PGA). The proposed a single-bit 2nd-order delta-sigma modulator has been implemented in a 350-nm CMOS process. It achieves 95.46-dB signal-to-noise-and-distortion ratio (SNDR), 96.01-dB spurious-free dynamic range (SFDR), and 15.56-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 400 for 5-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 670×490 ㎛2 and 414 ㎼, respectively.

• Journal of the Korean Magnetic Resonance Society
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• v.5 no.2
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• pp.99-109
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• 2001

Authors investigated neuronal changes of local cellular metabolism in the cerebral lesions of Parkinsonian symptomatic side between before and after stereotactic neurosurgery by follow-up 1H magnetic resonance spectroscopy (MRS). Patients with Parkinson's disease (PD) (n = 15) and age-matched normal controls (n = 15) underwen MRS examinations using a stimulated echo acquisition mode (STEAM) pulse sequence that provided 2${\times}$2${\times}$2 ㎤ (8ml) volume of interest in the regions of substantia nigra, thalamus, and lentiform nucleus. Spectral parameters were 20 ms TE, 2000 ms TR, 128 averages,2500 Hz spectral width, and 2048 data points. Raw data were processed by the SAGE data analysis package (GE Medical Systems). Peak areas of N-acetylaspartate (NAA), creatine (Cr), choline-containing compounds (Cho), inositols (Ins), and the sum (Glx) of glutamate and GABA were calculated by means of fitting the spectrum to a summation of Lorentzian curves using Marquardt algorithm. After blindly processed, we evaluated neuronal alterations of observable metabolite ratios between before and after stereotactic neurosurgery using Pearson product-moment analysis (SPSS, Ver. 6.0). A significant reduction of NAA/Cho ratio was observed in the cerebral lesion in substantia nigra of PD patient related to the symptomatic side after neurosurgery (P : 0.03). In thalamus, NAA/Cho ratio was also significantly decreased in the cerebral lesion including the electrode-surgical region (P : 0.03). A significant reduction of NAA/Cho ratio in lentiform nucleus was not oberved, but tended toward significant reduction after neurosurgery (P = 0.08). In particular, remarkable lactate signal was noted from the surgical thalamic lesions of 6 among 8 patients and internal segments of globus pallidus of 6 among 7 patients, respectively. Significant metabolic alterations of NAA/Cho ratio might reflect functional changes of neuropathological processes in the lesion of substantia nigra, thalamus, and lentiform nucleus, and could be a valuable finding fur evaluation of Parkinson's disease after neurosurgery. Increase of lactate signals, being remarkable in surgical lesions, could be consistent with a common consequence of neurosurgical necrosis. Thus, IH MRS could be a useful modality to evaluate the diagnostic and prognostic implications fur Parkinsons disease after functional neurosurgery.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.12
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• pp.1336-1347
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• 1991

In this paper, The PC interface for packet terminal of ISDN is designed and implemented in order to build packet communication networks which share computer resources and exchange informations between computer in the ISDN environment. The PC interface for packet terminal of ISDN constitutes S interface handler part which controls functions of ISDN layer1 and layer 2, constitutes packet handler part which controls services of X.25 protocol in the packet level.Where, The function of ISDN layer1 provides rules of electrical and mechanical characteristics, services for ISDN layer 2. The function of ISDN layer 2 provides function of LAPD procedure, services for X.25 The X.25 specifies interface between DCE and DTE for terminals operrating in the packet mode. The S interface handler part is orfanized by Am 79C30 ICs manufactured by Advanecd Micro Devices. ISDN packet handler part is organiged by AmZ8038 for FIFO for the purpose of D channel. The common signal procedure for D channel is controlled by Intel's 8086 microprocessor. The S interface handler part is based on ISDN layer1,2 is controlled by mail box in order to communicate between layers. The ISDN packet handler part is based on module in the X.25 lebel. The communication between S interface handler part and ISDN packet handler part is organized by interface controller.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.6
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• pp.454-464
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• 2023

This paper proposes a low-power 8-bit asynchronous SAR ADC with a sampling rate of 1 MS/s for sensor node applications. The ADC uses bootstrapped switches to improve linearity and applies a VCM-based CDAC switching technique to reduce the power consumption and area of the DAC. Conventional synchronous SAR ADCs that operate in synchronization with an external clock suffer from high power consumption due to the use of a clock faster than the sampling rate, which can be overcome by using an asynchronous SAR ADC structure that handles internal comparisons in an asynchronous manner. In addition, the SAR logic is designed using dynamic logic circuits to reduce the large digital power consumption that occurs in low resolution ADC designs. The proposed ADC was simulated in a 180-nm CMOS process, and at a 1.8 V supply voltage and a sampling rate of 1 MS/s, it consumed 46.06 𝜇W of power, achieved an SNDR of 49.76 dB and an ENOB of 7.9738 bits, and obtained a FoM of 183.2 fJ/conv-step. The simulated DNL and INL are +0.186/-0.157 LSB and +0.111/-0.169 LSB.