• Title/Summary/Keyword: common input

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A Study on Individual Tap-Power Estimation for Improvement of Adaptive Equalizer Performance

  • Kim, Nam-Yong
    • Journal of electromagnetic engineering and science
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    • v.4 no.1
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    • pp.23-29
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    • 2004
  • In this paper we analyze convergence constraints and time constant of IT-LMS algorithm and derive a method of making it's time constant independent of signal power by using input variance estimation. The method for estimating the input variance is to use a single-pole low-pass filter(LPF) with common smoothing parameter value, θ. The estimator is with narrow bandwidth for large θ but with wide bandwidth for small θ. This small θ gives long term average estimation(low frequency) of the fluctuating input variance well as short term variations (high frequency) of the input power. In our simulations of multipath communication channel equalization environments, the method with large θ has shown not as much improved convergence speed as the speed of the original IT-LMS algorithm. The proposed method with small θ=0.01 reach its minimum MSE in 100 samples whereas the IT-LMS converges in 200 samples. This shows the proposed, tap-power normalized IT-LMS algorithm can be applied more effectively to digital wireless communication systems.

Analysis of Transistorized Logarithmic Amplifier (트랜지스터 대수증폭기의 해석)

  • 이상배
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.6 no.1
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    • pp.19-22
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    • 1969
  • Detailed analysis has been developed concerning the transfer function and stability condition of the logarithmic amplifier using a common emitter transistor as a feed-back element. The analysis shows that input current vs output voltage transfer characteristics is accurately ogarithmic through entire operating current, and the time constant depends on input capcitance and collector-emitter equivalent resistance. Also the minimum value of imput capacitance required to stabilize the system is derived.

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A Study on the Response Characteristics of a High Speed Solenoid (고속 솔레노이드의 응답특성에 관한 연구)

  • Cho, Kyu-Hak
    • Journal of Fisheries and Marine Sciences Education
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    • v.12 no.2
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    • pp.142-151
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    • 2000
  • The studies on the electronic control fuel injection system for a DI diesel engine have done for reducing the exhaust emission and improving fuel consumption. The electronic control fuel injection system is classified into a common rail system, a unit injector system and a high pressure injection system. The characteristics of these systems are largely depends on the operating characteristics of its solenoid that have high speed on-off operation. In order to improve these characteristics of fuel injection system, it is necessary to design the optimal shape of solenoid and select the input method of its power source. It was proposed HELENOID, COLENOID, DISOLE, and Multipole Solenoid in the studies of design for the optimal shape of solenoid. The studies on the energizing method, input method for power of solenoid were dealt with the conventional energizing method, the chopping method and the pre-energizing method. In order to find out the high response characteristics of solenoid, it is necessary to test the performance of optimally designed solenoid with a new energizing method. In this paper, the solenoid of multi-pole type with plat armature and its power control unit to control input current by the chopping method designed, and its response tests were performed according to its energizing conditions. As a result, the maximum input current for solenoid was controlled by the period of first stage exciting current and chopping duty ratio of control stage exciting current, and the fastest "on" time was able to get 0.46ms. The conditions of fastest "on" time was 0.3ms for first stage exciting current, 0.16ms for control exciting current and 75% for chopping duty ratio.

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Reconfigurable CMOS low-noise amplifier for multi-mode/multi-band wireless receiver (다중모드/다중대역 무선통신 수신기를 위한 재구성 가능 CMOS 저잡음 증폭기)

  • Hwang, Bo-Hyun;Jung, Jae-Hoon;Kim, Shin-Nyoung;Jeong, Chan-Young;Lee, Mi-Young;Yoo, Chang-Sik
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.10 s.352
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    • pp.111-117
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    • 2006
  • Reconfigurable CMOS low-noise amplifier (LAN) has been developed for multi-mode/multi-band wireless receiver. By employing common-gate input stage, the performance can be optimized for multiple operation bands by simply controlling the output load impedance. Although the conventional common-gate LAN has larger than 3dB noise figure (NF), the newly developed negative feedback scheme enables the common-gate input LNA to have less than 2dB NF. To have optimum linearity performance of wireless receiver, the gain of the LNA can be controlled. The LNA implemented in a 0.13mm CMOS technology shows $19{\sim}20dB$ voltage gain, $1.7{\sim}2.0dB$ NF, -2dBm iIP3 at $1.8{\sim}2.5GHz$ frequency range. The LNA dissipates 7mW from a 1.2V supply voltage.

Design of a Linear CMOS OTA with Mobility Compensation and Common-Mode Control Schemes (이동도 보상 회로와 공통모드 전압 조절기법을 이용한 선형 CMOS OTA)

  • Kim, Doo-Hwan;Yang, Sung-Hyun;Kim, Ki-Sun;Cho, Kyoung-Rok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.12 s.354
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    • pp.81-88
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    • 2006
  • This paper describes a new linear operational transconductance amplifier (OTA). To improve the linearity of the OTA, we employ a mobility compensation circuit that combines the transistor paths operating at the triode and subthreshold regions. The common-mode control schemes consist of a common-mode feedback (CMFB) and common-mode feedforward (CMFF). The circuit enhances linearity of the transconductance (Gm) under the wide input voltage swing range. The proposed OTA shows ${\pm}1%$ Gm variation and the total harmonic distortion (THD) of below -73dB under the input voltage swing range of ${\pm}1.1V$. The OTA is implemented using a $0.35{\mu}m$ n-well CMOS process under 3.3V supply.

Design and Fabrication of 0.25 μm CMOS TIA Using Active Inductor Shunt Peaking (능동형 인덕터 Shuut Peaking을 이용한 0.25 μm CMOS TIA 설계 및 제작)

  • Cho In-Ho;Lim Yeongseog
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.16 no.9 s.100
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    • pp.957-963
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    • 2005
  • This paper presents technique of wideband TIA for optical communication systems using TSMC 0.25 ${\mu}m$ CMOS RF-Mixed mode. In order to improve bandwidth characteristics of an TIA, we use active inductor shunt peaking to cascode and common-source configuration. The result shows the 37 mW and 45 mW power dissipation with 2.5 V bias and 61 dB$\Omega$ and 61.4 dB$\Omega$ transimpedance gain. And the -3 dB bandwidth of the TIA is enhanced from 0.8 GHz to 1.45 GHz in cascode and 0.61 GHz to 0.9 GHz in common-source. And the input noise current density is $5 pA/\sqrt{Hz}$ and $4.5 pA/\sqrt{Hz}$, and -10 dB out put return loss is obtained in 1.45 GHz. The total size of the chip is $1150{\times}940{\mu}m^2$.

High Noise Margin LVDS I/O Circuits for Highly Parallel I/O Environments (다수의 병렬 입.출력 환경을 위한 높은 노이즈 마진을 갖는 LVDS I/O 회로)

  • Kim, Dong-Gu;Kim, Sam-Dong;Hwang, In-Seok
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.44 no.1
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    • pp.85-93
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    • 2007
  • This paper presents new LVDS I/O circuits with a high noise margin for use in highly parallel I/O environments. The proposed LVDS I/O includes transmitter and receiver parts. The transmitter circuits consist of a differential phase splitter and a output stage with common mode feedback(CMFB). The differential phase splitter generates a pair of differential signals which have a balanced duty cycle and $180^{\circ}$ phase difference over a wide supply voltage variation due to SSO(simultaneous switching output) noises. The CMFB output stage produces the required constant output current and maintains the required VCM(common mode voltage) within ${\pm}$0.1V tolerance without external circuits in a SSO environment. The proposed receiver circuits in this paper utilizes a three-stage structure(single-ended differential amp., common source amp., output stage) to accurately receive high-speed signals. The receiver part employs a very wide common mode input range differential amplifier(VCDA). As a result, the receiver improves the immunities for the common mode noise and for the supply voltage difference, represented by Vgdp, between the transmitter and receiver sides. Also, the receiver produces a rail-to-rail, full swing output voltage with a balanced duty cycle(50% ${\pm}$ 3%) without external circuits in a SSO environment, which enables correct data recovery. The proposed LVDS I/O circuits have been designed and simulated with 0.18um TSMC library using H-SPICE.

An Input-Powered High-Efficiency Interface Circuit with Zero Standby Power in Energy Harvesting Systems

  • Li, Yani;Zhu, Zhangming;Yang, Yintang;Zhang, Chaolin
    • Journal of Power Electronics
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    • v.15 no.4
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    • pp.1131-1138
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    • 2015
  • This study presents an input-powered high-efficiency interface circuit for energy harvesting systems, and introduces a zero standby power design to reduce power consumption significantly while removing the external power supply. This interface circuit is composed of two stages. The first stage voltage doubler uses a positive feedback control loop to improve considerably the conversion speed and efficiency, and boost the output voltage. The second stage active diode adopts a common-grid operational amplifier (op-amp) to remove the influence of offset voltage in the traditional comparator, which eliminates leakage current and broadens bandwidth with low power consumption. The system supplies itself with the harvested energy, which enables it to enter the zero standby mode near the zero crossing points of the input current. Thereafter, high system efficiency and stability are achieved, which saves power consumption. The validity and feasibility of this design is verified by the simulation results based on the 65 nm CMOS process. The minimum input voltage is down to 0.3 V, the maximum voltage efficiency is 99.6% with a DC output current of 75.6 μA, the maximum power efficiency is 98.2% with a DC output current of 40.4 μA, and the maximum output power is 60.48 μW. The power loss of the entire interface circuit is only 18.65 μW, among which, the op-amp consumes only 2.65 μW.

A Study on the Fisheries Control System of the Fisheries Act of Korea (수산관련법상(水產關聯法上) 어업관리제도(漁業管理制度)에 관한 연구(硏究))

  • Lee, Zong-Keun
    • Journal of Fisheries and Marine Sciences Education
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    • v.11 no.1
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    • pp.1-23
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    • 1999
  • The fisheries control system being now enforced in all countries may be generally classified as three types - the input control system, the output control system, and the technical control system. In Asian countries that have relatively small fishery scales, diverse object species and the fisheries resources has been regarded as "governmental possessions", fisheries have been controled subsidiarily using the technical control system based on the input control system traditionally. While in Europe and America that have relatively large fisheries scales, simple object species and the fisheries resources has been regarded as "common property", fisheries have been controled subsidiarily using the input control system and the technical control system based on the output control system. In Korea, fisheries have been controled subsidiarily using the technical control system based on the input control system traditionally, nevertheless overexplotation and overcapitalization have not been solved. Recently the EEZ was promulgated, the total allowable catch system was introduced to control the EEZ. But the output control system is totally different from the input control system of the Korea traditional fisheries system, simultaneous availableness of both system is considerably difficulty. Therefore a study on new systems to make both systems harmonized has to be performed. The thesis is aimed at presenting the general improvement direction of the Korea fisheries control system as the basis for establishment of the new fisheries control system.

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Recognition of Superimposed Patterns with Selective Attention based on SVM (SVM기반의 선택적 주의집중을 이용한 중첩 패턴 인식)

  • Bae, Kyu-Chan;Park, Hyung-Min;Oh, Sang-Hoon;Choi, Youg-Sun;Lee, Soo-Young
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.42 no.5 s.305
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    • pp.123-136
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    • 2005
  • We propose a recognition system for superimposed patterns based on selective attention model and SVM which produces better performance than artificial neural network. The proposed selective attention model includes attention layer prior to SVM which affects SVM's input parameters. It also behaves as selective filter. The philosophy behind selective attention model is to find the stopping criteria to stop training and also defines the confidence measure of the selective attention's outcome. Support vector represents the other surrounding sample vectors. The support vector closest to the initial input vector in consideration is chosen. Minimal euclidean distance between the modified input vector based on selective attention and the chosen support vector defines the stopping criteria. It is difficult to define the confidence measure of selective attention if we apply common selective attention model, A new way of doffing the confidence measure can be set under the constraint that each modified input pixel does not cross over the boundary of original input pixel, thus the range of applicable information get increased. This method uses the following information; the Euclidean distance between an input pattern and modified pattern, the output of SVM, the support vector output of hidden neuron that is the closest to the initial input pattern. For the recognition experiment, 45 different combinations of USPS digit data are used. Better recognition performance is seen when selective attention is applied along with SVM than SVM only. Also, the proposed selective attention shows better performance than common selective attention.