• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.10
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• pp.615-619
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• 2005

Token coherence protocol has many good reasons against snooping/directory-based protocol in terms of latency, bandwidth, and complexity. Token counting easily maintains correctness of the protocol without global ordering of request which is basis of other dominant cache coherence protocols. But this lack of global ordering causes starvation which is not happening in snooping/directory-based protocols. Token coherence protocol solves this problem by providing an emergency mechanism called persistent request. It enforces other processors in the competition (or accessing same shared memory block, to give up their tokens to feed a starving processor. However, as the number of processors grows in a system, the frequency of starvation occurrence increases. In other words, the situation where persistent request occurs becomes too frequent to be emergent. As the frequency of persistent requests increases, not only the cost of each persistent matters since it is based on broadcasting to all processors, but also the increased traffic of persistent requests will saturate the bandwidth of multiprocessor interconnection network. This paper proposes a new request mechanism that defines order of requests to reduce occurrence of persistent requests. This ordering mechanism has been designed to be decentralized since centralized mechanism in both snooping-based protocol and directory-based protocol is one of primary reasons why token coherence protocol has advantage in terms of latency and bandwidth against these two dominant Protocols.

• Journal of IKEEE
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• v.8 no.2 s.15
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• pp.207-215
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• 2004

In a hierarchical-bus multiprocessor system, cache coherence protocol has effect on system performance. Under a particular cache coherence protocol, system performance can be affected by bus bandwidth, memory size, and memory block size. Therefore sensitivity analysis is necessary for the part of multiprocessor system. In this paper, we set up cache coherence protocol for hierarchical-bus multiprocessor system, and compute probability of state of protocol, and analyze sensitivity for part of system by simulation.

• The Transactions of the Korea Information Processing Society
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• v.2 no.5
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• pp.757-767
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• 1995

In this paper, we present MI-MESI write-invalidate snooping cache coherence protocol which addresses several significant drawbacks of MESI and MI-MESI write -invalidate snooping cache coherence protocols under the split transaction bus based multiprocessor environment. In this protocol, each cache block maintains one of six cache states which represent Modified-shared, Invalid-by-other, Modified, Exclusive, Shared and Invalid states. By using these cache states, our protocol reduces both the access contention and unnecessary updates for the memory modules significantly, and thus providing the fast memory access time.

• Journal of the Korea Society of Computer and Information
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• v.11 no.6 s.44
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• pp.125-131
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• 2006

This Paper proposes a new directory-based cache coherence scheme which significantly reduces coherence traffic by omitting unnecessary write-backs to home nodes for migratory exclusively-modified data. The proposed protocol is well matched to such migratory data which are accessed in turn by processors, since write-backs to home nodes are never used for such migratory sharing. The simulation result shows that our protocol dramatically alleviate the coherence traffic, and the traffic reduction could also lead to shorten network latency and execution time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.4A
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• pp.310-315
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• 2002

The Bark Coherence Function (BCF) defies a coherence function within perceptual domain as a new cognition module, robust to linear distortions due to the analog interface of digital mobile system. Our previous experiments have shown the superiority of BCF over current measures. In this paper, a new BCF suitable for VoIP is developed. The unproved BCF is based on the wavelet series expansion that provides good frequency resolution while keeping good time locality. The proposed Wavelet based Bark Coherence function (WBCF) is robust to variable delay often observed in packet-based telephony such as Voice over Internet Protocol (VoIP). We also show that the refinement of time synchronization after signal decomposition can improve the performance of the WBCF. The regression analysis was performed with VoIP speech data. The correlation coefficients and the standard error of estimates computed using the WBCF showed noticeable improvement over the Perceptual Speech Quality Measure (PSQM) that is recommended by ITU-T.

• The Transactions of the Korea Information Processing Society
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• v.7 no.7
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• pp.2219-2228
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• 2000

Caches in a multiprocessing environment introduce the cache coherence problem. When multiple processors maintain locally cached copies of a unique shared-memory location, any local modification of the location can result in a globally inconsistent view of memory. Cache coherence protocols are important to operate a shared-memory multiprocessor system with efficiency and correctness. Since random testing and simulations are not enough to validate correctness of protocols, it is necessary to develop efficient and reliable verification methods. In this appear we present our experience in using VIS (Verification Interacting with Synthesis), a tool of formal method, to analyze a number of property of a cache coherence protocol, RACE (Remote Access Cache coherent Enforcement).

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.39 no.3
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• pp.1-17
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• 2002

In this paper, we present our experiences in using symbolic model checker(SMV) to analyze a number of properties of RACE cache coherence protocol designed by ETRI(Electronics and Communications Research Institute) and to verify that RACE protocol satisfies important requirements. To investigate this, we specified the model of the RACE protocol as the input language of SMV and specified properties as a formula in temporal logic CTL. We successfully used the symbolic model checker to analyze a number of properties of RACE protocol. We verified that abnormal state/input combinations was not occurred and every possible request of processors was executed correctly We verified that RACE protocol satisfies liveness, safety and the property that any abnormal state/input combination was never occurred. Besides, We found some ambiguities of the specification and a case of starvation that the protocol designers could not expect before. By this verification experience, we show advantages of model checking method. And, we propose a new method to generate automatically test cases which are used in simulation and testing.

• Journal of the Semiconductor & Display Technology
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• v.23 no.1
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• pp.65-70
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• 2024

Direct cache-to-cache transfer has been studied to reduce the latency and bandwidth consumption related to the shared data in multiprocessor system. Even though these studies lead to meaningful results, they assume that caches consist of SRAM. For example, if the system employs the non-volatile memory, the one of the most important parts to consider is to decrease the number of write operations. This paper proposes a hybrid write avoidance cache coherence protocol that considers the hybrid cache architecture. A new state is added to finely control what is stored in the non-volatile memory area, and experimental results showed that the number of writes was reduced by about 36% compared to the existing schemes.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1990.06a
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• pp.832-836
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• 1990

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.12
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• pp.1815-1827
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• 1993

In this paper, we evaluate the performance of a Futurebus based multiprocessor system with MESI cache coherence protocol for four bus transaction types. Graphical symbols and compiler of SLAM II are used in modeling and simulation. A steady-state probability of each state for MESI protocol is computed by a Markov chain. The probability of each state is used as an input value for a correct simulation. Processor utilization, memory utilization, bus utilization, and the waiting time for bus arbitration are measured in terms of the number of processors, the hit ratio of cache memory, the probability of internal operation, and bus bandwidth.