• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.333-336
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• 2002

In many cases, fuzzy modeling has a defect that the design procedure cannot be theoretically justified. To overcome this difficulty, we suggest a new design method for fuzzy model by combining genetic algorithm(GA) and mush set theory. GA, which has the advantages is optimization, and rule base. However, it is some what time consuming, so are introduce rough set theory to the rule reduction procedure. As a result, the decrease of learning time and the considerable rate of rule reduction is achieved without loss of useful information. The preposed algorithm is composed of three stages; First stage is quasi-optimization of fuzzy model using GA(coarse tuning). Next the obtained rule base is reduced by rough set concept(rule reduction). Finally we perform re-optimization of the membership functions by GA(fine tuning). To check the effectiveness of the suggested algorithm, examples for time series prediction are examined.

• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2120-2122
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• 2002

There are several types of control systems that use fuzzy logic controller as a essential system component. The majority of research work on fuzzy PID controller focuses on the conventional two-input PI or PD type controller. However, fuzzy PID controller design is a complex task due to the involvement of a large number of parameters in defining the fuzzy rule base. In this paper we combined conventional PI type and PD type fuzzy controller and set the initial parameters of this controller from the conventional PID controller gains obtained by Ziegler-Nichols tuning or other coarse tuning methods. After that, by replacing some of these parameters with sing1e neurons and making them to be adjusted by back-propagation learning algorithm we designed a neuro-fuzzy controller which showed good performance characteristics in both computer simulation and actual application.

• Proceedings of the Optical Society of Korea Conference
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• 2002.07a
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• pp.188-189
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• 2002

기간망의 속도 증가와 더불어 가입자망치 고속화는 필수 불가결한 것으로 이를 위해 메트로 네트웍의 고속화에 대한 노력이 진행되고 있다. 메트로 네트웍 및 가입자망의 고속화를 위해서는 시스템의 저가화가 필요하다. CWDM(Coarse WDM)은 채널 간격이 10 - 25nm로 채널 간격이 넓기 때문에 복잡한 온도제어 없이 저가의 Uncooled DFB-LD 및 WDM 소자를 사용할 수 있어서, 메트로 네트웍의 대용량화를 보다 경제적으로 실현가능하기 때문에 CWDM 시스템이 유망한 것으로 받아들여지고 있다. (중략)

• Journal of the Korean Institute of Intelligent Systems
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• v.12 no.4
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• pp.334-340
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• 2002

This paper proposes a self-organizing fuzzy modeling which can create a new hyperplane-shaped cluster by applying multiple regression to input/output data with relatively large fuzzy entropy, add the new cluster to fuzzy rule base and adjust parameters of the fuzzy model in repetition. Tn the coarse tuning, weighted recursive least squared algorithm and fuzzy C-regression model clustering are used and in the fine tuning, gradient descent algorithm is used to adjust parameters of the fuzzy model precisely And learning rates are optimized by utilizing meiosis-genetic algorithm. To check the effectiveness and feasibility of the suggested algorithm, four representative examples for system identification are examined and the performance of the identified fuzzy model is demonstrated in comparison with that of the conventional fuzzy models.

• Journal of electromagnetic engineering and science
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• v.9 no.1
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• pp.25-31
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• 2009

This paper describes CMOS VCO circuit design procedures and techniques for multi-band/multi-standard RF transceivers. The proposed techniques enable a 4 GHz CMOS VCO to satisfy all requirements for Quad-band GSMIEDGE and WCDMA standards by achieving a good trade-off among important specifications, phase noise, power consumption, modulation performance, and chip area efficiency. To meet the very stringent GSM T/Rx phase noise and wide frequency range specifications, the VCO utilizes bond-wire inductors with high-quality factor, an 8-bit coarse tune capbank for low VCO gain(30$\sim$50 MHz/V) and an on-chip $2^{nd}$ harmonic noise filter. The proposed VCO is implemented in $0.13{\mu}m$ CMOS technology. The measured tuning range is about 34 %(3.17 to 4.49 GHz). The VCO exhibits a phase noise of -123 dBc/Hz at 400 kHz offset and -145 dBc/Hz at 3 MHz offset from a 900 MHz carrier after LO chain. The calculated figure of merit(FOM) is -183.5 dBc/Hz at 3 MHz offset. This fully integrated VCO occupies $0.45{\times}0.9\;mm^2$.

• Journal of IKEEE
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• v.15 no.1
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• pp.29-36
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• 2011

Dithering scheme has been widely used to improve the resolution of DCO(Digitally Controlled Oscillator) in conventional ADPLLs(All Digital Phase Locked Loop). In this paper a new resolution improvement scheme is proposed where a simple DAC is employed to overcome the problems of dithering scheme. A 2.4GHz LC-based DCO has been designed in a $0.13{\mu}m$ CMOS process with an enhanced frequency resolution for wireless local area network applications. It has a frequency tuning range of 900MHz and a resolution of 58.8Hz. The frequencies are controled by varactors in coarse, fine, and DAC bank. The DAC bank consists of an inversion mode NMOS varactor. The other varactor banks consist of PMOS varactors. Each varactor bank is controlled by 8bit digital signal. The designed DCO exhibits a phase noise of -123.8dBc/Hz at 1MHz frequency offset. The DCO core consumes 4.2mA from 1.2V supply.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.7
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• pp.1543-1551
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• 2011

Dithering scheme has been widely used to improve the resolution of DCO(Digitally Controlled Oscillator) in conventional ADPLLs(All Digital Phase Locked Loop). In this paper a new resolution improvement scheme is proposed where a simple DAC(Digital-to-Analog Converter) is employed to overcome the problems of dithering scheme. The frequencies are controled by varactors in coarse, fine, and DAC bank. The DAC bank consists of an inversion mode NMOS varactor. The other varactor banks consist of PMOS varactors. Each varactor bank is controlled by 8bit digital signal. The proposed DCO has been designed in a $0.13{\mu}m$ CMOS process. Measurement results shows that the designed DCO oscillates in 2.8GHz~3.5GHz and has a frequency tuning range of 660MHz and a resolution of 73Hz at 2.8GHz band. The designed DCO exhibits a phase noise of -119dBc/Hz at lMHz frequency offset. The DCO core consumes 4.2mA from l.2V supply. The chip area is $1.3mm{\times}1.3mm$ including pads.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.8
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• pp.964-969
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• 2007

A regulated low phase noise differential colpitts VCO(Voltage Controlled Oscillator) for mobile RFID system is presented. The differential colpitts VCO meets the dense reader environment specifications. The VCO use a $0.35{\mu}m$ technology and achieves tuning range $1.55{sim}2.053 GHz$. Measuring 910 MHz frequency divider output, phase noise performance is -106 dBcMz and -135dBc/Hz at 40 kHz and 1MHz offset, respectively. 5-bit digital coarse-tuning and accumulation type MOS varactors allow for 28.2% tuning range, which is required to cover the LO frequency range of a UHF Mobile RFID system, Optimum design techniques ensure low VCO gain(<45 MHz/V) for good interoperability with the frequency synthesizer. To the author' knowledge, this differential colpitts VCO achieves a figure of merit(FOM) of 1.93dB at 2-GHz band.

• Korean Journal of Optics and Photonics
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• v.17 no.3
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• pp.273-277
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• 2006

In this paper, we constructed the Littman type and fixed Littrow type tunable external-cavity diode laser systems. The laser output, which is the 0th-order diffracted beam from the diffraction grating in an external cavity, was the single longitudinal mode. Its FWHM was measured as less than 9MHz. With the diode driving current of 140mA and operating temperature of $25^{\circ}C$, the coarse tuning range of 5.375nm was measured for the Littman type, and of 13.65nm was measured for the fixed Littrow type. A fine tuning experiment in which an external mirror was rotated by a PZT driven by a sawtooth wave was performed, and its tuning range of 0.042nm was measured for both types. The fixed Littrow type tunable external-cavity diode laser system was an improvement on the conventional Littrow type tunable laser system in which the output direction varies due to the grating embedded in the mirror plate.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.117-124
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• 2009

This paper describes a 3 to 5 GHz frequency synthesizer for MB-OFDM (Multi-Band OFDM) UWB (Ultra- Wideband) application using 0.13 ${\mu}m$ CMOS process. The frequency synthesizer operates in the band group 1 whose center frequencies are 3432 MHz 3960 MHz, and 4488 MHz. To cover the overall frequencies of group 1, an efficient frequency planning minimizing a number of blocks and the power consumption are proposed. And, a high-frequency VCO and LO Mixer architecture are also presented in this paper. A new mixed coarse tuning scheme that utilizes the MIM capacitance, the varactor arrays, and the DAC is proposed to expand the VCO tuning range. The frequency synthesizer can also provide the clock for the ADC in baseband modem. So, the PLL for the ADC in the baseband modem can be removed with this frequency synthesizer. The single PLL and two SSB-mixers consume 60 mW from a 1.2 sV supply. The VCO tuning range is 1.2 GHz. The simulated phase noise of the VCO is -112 dBc/Hz at 1 MHz offset. The die area is 2 ${\times}$ 2mm$^2$.