• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 하계학술대회 논문집 B
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• pp.1268-1270
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• 1993

In this study, the characteristics of Si-$SiO_2$ interface and its degradation in short channel SONOSFET nonvolatile memory devices, fabricated by 1Mbit CMOS process($1.2{\mu}m$ design rule), with $65{\AA}$ blocking oxide layer, $205{\AA}$ nitride layer, and $30{\AA}$ tunneling oxide layer on the silicon wafer were investigated using the charge pumping method. For investigating the Si-$SiO_2$ interface characteristics before and after write/erase cycling, charge pumping current characteristics with frequencies, write/erase cycles, as a parameters, were measured. As a result, average Si-$SiO_2$ interface trap density and mean value of capture cross section were determined to be $1.203{\times}10^{11}cm^{-2}eV^{-1}\;and\;2.091{\times}10^{16}cm^2$ before write/erase cycling, respectively. After cycling, when the write/erase cycles are $10^4$, average $Si-SiO_2$ interface trap density was $1.901{\times}10^{11}cm^{-2}eV^{-1}$. Incresing write/erase cycles beyond about $10^4$, Si-$SiO_2$ interface characteristics with write/erase cycles was increased logarithmically.

• 한국진공학회지
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• 제20권3호
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• pp.182-188
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• 2011

탄소가 없는 폴리실라잔 계와 탄소가 함유된 폴리메틸 실라잔 계 전구체를 실리콘 기판에 스핀코팅하고 $150^{\circ}C$, $400^{\circ}C$, $850^{\circ}C$에서 열처리하여 형성된 박막의 물리적 화학적 특성을 평가하였다. 프리에 변환 적외선 분광, 수축 율, 갭-충진, 식각속도 등을 평가하여 박막형성과 형성된 박막의 물리화학적 특성에 미치는 탄소의 영향을 고찰하였다. 탄소함유 전구체는 (탄소가 없는 전구체보다) $400^{\circ}C$에서 질소, 수소, 탄소의 휘발량이 더 적고 산소 흡수량이 더 적어서 (15.6%)보다 낮은 14.5% 두께 수축을 나타내었으나, $800^{\circ}C$에서는 휘발 량이 더 많고 산소 흡수량도 더 많아져 (19.4%)보다 높은 37.4% 두께 수축을 나타냈다. 프리에 변환 적외선 분광분석결과, 전구체내의 탄소는 Spin-on dielectric (SOD) 박막으로 하여금 Si-O 결합형성을 적게, 박막특성을 불균일하게, 그리고 화학 용액에 더 빨리 식각되도록 만들었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
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• pp.214.2-214.2
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• 2013

Device performance for the 45 and 32 nm node CMOS technology requires the integration of ultralow-k materials. To lower the dielectric constant for PECVD and spin-on materials, partial replacement of the solid network with air (k=1.01) appears to be more intuitive and direct option. This can be achieved introducting of second "labile" phase during depositoin that is removed during a subsequent UV curing and annealing step. Besides, with shrinking line dimensions the resistivity of barrier films cannot meet the International Technology Roadmap for Semiconductors (ITRS) requirements. To solve this issue self-forming diffusion barriers have drawn attention for great potential technique in meeting all ITRS requirments. In this present work, we report a Cu-V alloy as a materials for the self-forming barrier process. And we investigated diffusion barrier properties of self-formed layer on low-k dielectrics with or without UV curing treatment. Cu alloy films were directly deposited onto low-k dielectrics by co-sputtering, followed by annealing at various temperatures. X-ray diffraction revealed Cu (111), Cu (200) and Cu (220) peaks for both of Cu alloys. The self-formed layers were investigated by transmission electron microscopy. In order to compare barrier properties between V-based interlayer on low-k dielectric with UV curing and interlayer on low-k dielectric without UV curing, thermal stability was measured with various heat treatment temperature. X-ray photoelectron spectroscopy analysis showed that chemical compositions of self-formed layer. The compositions of the V based self-formed barriers after annealing were strongly dominated by the O concentration in the dielectric layers.

• 한국소음진동공학회:학술대회논문집
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• 한국소음진동공학회 2013년도 추계학술대회 논문집
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• pp.763-764
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• 2013

A three-dimensional image capturing device and its signal processing algorithm and apparatus are presented. Three dimensional information is one of emerging differentiators that provides consumers with more realistic and immersive experiences in user interface, game, 3D-virtual reality, and 3D display. It has the depth information of a scene together with conventional color image so that full-information of real life that human eyes experience can be captured, recorded and reproduced. 20 Mega-Hertz-switching high speed image shutter device for 3D image capturing and its application to system prototype are presented[1,2]. For 3D image capturing, the system utilizes Time-of-Flight (TOF) principle by means of 20MHz high-speed micro-optical image modulator, so called 'optical resonator'. The high speed image modulation is obtained using the electro-optic operation of the multi-layer stacked structure having diffractive mirrors and optical resonance cavity which maximizes the magnitude of optical modulation[3,4]. The optical resonator is specially designed and fabricated realizing low resistance-capacitance cell structures having small RC-time constant. The optical shutter is positioned in front of a standard high resolution CMOS image sensor and modulates the IR image reflected from the object to capture a depth image (Figure 1). Suggested novel optical resonator enables capturing of a full HD depth image with depth accuracy of mm-scale, which is the largest depth image resolution among the-state-of-the-arts, which have been limited up to VGA. The 3D camera prototype realizes color/depth concurrent sensing optical architecture to capture 14Mp color and full HD depth images, simultaneously (Figure 2,3). The resulting high definition color/depth image and its capturing device have crucial impact on 3D business eco-system in IT industry especially as 3D image sensing means in the fields of 3D camera, gesture recognition, user interface, and 3D display. This paper presents MEMS-based optical resonator design, fabrication, 3D camera system prototype and signal processing algorithms.

• 한국정보통신학회논문지
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• 제12권6호
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• pp.1056-1063
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• 2008

부호화율과 구속장을 선택적으로 지정할 수 있는 다중 표준용 파라미터화된 비터비 복호기의 효율적인 설계에 대해 기술한다. 설계된 비터비 복호기는 부호화율 1/2과 1/3, 구속장 7과 9를 지원하여 4가지 모드로 동작하도록 파라미터화된 구조로 설계되었으며, 각 동작모드에서 공통으로 사용되는 블록들의 공유가 극대화되는 회로구조를 적용하여 면적과 전력소모가 최소화되도록 하였다. 또한, one-point 역추적 알고리듬에 최적화된 ACCS (Accumulate-Subtract) 회로를 적용하였으며, 이를 통해 완전 병렬구조에 비해 ACCS 회로의 면적을 약 35% 감소시켰다. 설계된 비터비 복호기 코어는 0.35-um CMOS 셀 라이브러리로 합성하여 79,818 게이트와 25,600비트의 메모리로 구현되었으며, 70 MHz 클록으로 동작하여 105 Mbps의 성능을 갖는다. 설계된 비터비 복호기의 BER (Bit Error Rate) 성능에 대한 시뮬레이션 결과, 부호화율 1/3과 구속장 7로 동작하는 경우에 3.6 dB의 $E_b/N_o$에서 $10^{-4}$의 비트 오류율을 나타냈다.

• 방사선산업학회지
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• 제9권1호
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• pp.1-7
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• 2015

The trend of x-ray image sensor has been evolved from an amorphous silicon sensor to a crystal silicon sensor. A crystal silicon X-ray sensor, meaning a X-ray CIS (CMOS image sensor), is consisted of three transistors (Trs), i.e., a Reset Transistor, a Source Follower and a Select Transistor, and a photodiode. They are highly sensitive to radiation exposure. As the frequency of exposure to radiation increases, the quality of the imaging device dramatically decreases. The most well known effects of a X-ray CIS due to the radiation damage are increments in the reset voltage and dark currents. In this study, a pixel array of a X-ray CIS was made of $20{\times}20pixels$ and this pixel array was exposed to a high radiation dose. The radiation source was Co-60 and the total radiation dose was increased from 1 to 9 kGy with a step of 1 kGy. We irradiated the small pixel array to get the increments data of the reset voltage and the dark currents. Also, we simulated the radiation effects of the pixel by MCNP (Monte Carlo N-Particle) simulation. From the comparison of actual data and simulation data, the most affected location could be determined and the cause of the increments of the reset voltage and dark current could be found.

• Current Optics and Photonics
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• 제2권5호
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• pp.422-430
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• 2018

Rolling shutter operation of CMOS cameras can be utilized in optical camera communications in order to transmit data from an LED to mobile devices such as smart-phones. From temporally modulated light, a spatial flicker pattern is obtained in the captured image, and this is used for signal recovery. Due to the degradation of rolling shutter images caused by light smear, motion blur, and focus blur, the conventional decoding schemes for rolling shutter cameras based on the pattern width for 'OFF' and 'ON' cannot guarantee robust communications performance for practical uses. Aside from conventional techniques, such as polynomial fitting, histogram equalization can be used for blurry light mitigation, but it requires additional computation abilities resulting in burdens on mobile devices. This paper proposes a transition-based decoding scheme for rolling shutter cameras in order to offer simple and robust data decoding in the presence of image degradation. Based on the designed synchronization pulse and modulated data symbols according to the LED dimming level, the decoding process is conducted by observing the transition patterns of two sequential symbol pulses. For this, the extended symbol pulse caused by consecutive symbol pulses with the same level determines whether the second pulse should be included for the next bit decoding or not. The proposed method simply identifies the transition patterns of sequential symbol pulses other than the pattern width of 'OFF' and 'ON' for data decoding, and thus, it is simpler and more accurate. Experimental results ensured that the transition-based decoding scheme is robust even in the presence of blurry lights in the captured image at various dimming levels

• 한국정보통신학회논문지
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• 제25권9호
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• pp.1158-1165
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• 2021

본 논문은 메모리의 사이즈를 줄이기 위해 Pooling Layer가 MAC에 통합된 구조의 최적화된 CNN가속기를 설계하는 것을 제안한다. 메모리와 데이터 전달 회로의 최소화를 위해 MNIST를 이용하여 학습된 32bit 부동소수점 가중치 값을 8bit로 양자화하여 사용하였다. 가속기칩 크기의 최소화를 위해 MNIST용 CNN 모델을 1개의 Convolutional layer, 4*4 Max Pooling, 두 개의 Fully connected layer로 축소하였고 모든 연산에는근사화 덧셈기와 곱셈기가 들어간 특수 MAC을 사용한다. Convolution 연산과 동시에 Pooling이 동작하도록 설계하여 내장 메모리를 94% 만큼 축소하였으며, pooling 연산의 지연 시간을 단축했다. 제안된 구조로 MNIST CNN 가속기칩을 TSMC 65nm GP 공정으로 설계한 결과 기존 연구결과의 절반 크기인 0.8mm x 0.9mm = 0.72mm²의 초소형 가속기 설계 결과를 도출하였다. 제안된 CNN 가속기칩의 테스트 결과 94%의 높은 정확도를 확인하였으며, 100MHz 클럭 사용시 MNIST 이미지당 77us의 빠른 처리 시간을 획득하였다.

• 한국정보통신학회논문지
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• 제23권7호
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• pp.822-828
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• 2019

증강현실은 실제 환경과 함께 가상 정보를 제공하며, 이러한 시스템을 위해 프로세서의 메모리 접근이 요구된다. 하지만 기술 발전에 따라 데이터의 양이 증가함으로써, 프로세서의 작업량 또한 증가하게 된다. 이를 해결하기 위해 임베디드 프로세서의 작업 부하를 감소시킬 수 있는 특정 모듈을 필요로 한다. 본 논문에서는 임베디드 프로세서 대신에 이미지를 출력하는 Direct Memory Acceass(DMA) 컨트롤러를 제안한다. 제안하는 DMA 컨트롤러를 Field Programmable Gate Array(FPGA)에 구현하고 Avalon Memory Mapped(Avalon-MM) 인터페이스를 기반으로 한 DMA 컨트롤러의 기능을 시연한다. 또한, DMA 컨트롤러를 Magnachip/Hynix 0.35um CMOS로 제작하고, 임베디드 시스템의 실현 가능성을 검증한다.

• 전기전자학회논문지
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• 제23권3호
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• pp.917-924
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• 2019

This paper presents a wideband low noise amplifier (LNA) that is suitable for LTE-Advanced and 5G communication standards employing carrier aggregation (CA). The proposed LNA encompasses a common input stage and a dual output second stage with a buffer at each distinct output. This architecture is targeted to operate in both intra-band (contiguous and non-contiguous) and inter-band CA. In the proposed design, the input and second stages employ a gm enhancement with resistive feedback technique to achieve self-biasing, enhanced gain, wide bandwidth as well as reduced noise figure of the proposed LNA. An up/down power controller controls the single input single out (SISO) and single input multiple outputs (SIMO) modes of operation for inter-band and intra-band operations. The proposed LNA is designed with a 45nm CMOS technology. For SISO mode of operation, the LNA operates from 0.52GHz to 4.29GHz with a maximum power gain of 17.77dB, 2.88dB minimum noise figure and input (output) matching performance better than -10dB. For SIMO mode of operation, the proposed LNA operates from 0.52GHz to 4.44GHz with a maximum voltage gain of 18.30dB, a minimum noise figure of 2.82dB with equally good matching performance. An $IIP_3$ value of -6.7dBm is achieved in both SISO and SIMO operations. with a maximum current of 42mA consumed (LNA+buffer in SIMO operation) from a 1.2V supply.