• The Journal of the Acoustical Society of Korea
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• v.19 no.1
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• pp.84-88
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• 2000

In this paper, a low voltage CMOS analog four-quadrant multiplier is presented. The proposed multiplier is composed of two fully differential transconductors and lowers supply voltage down to VT+2VDS,sat+VDS,triode. The designed analog four-quadrant multiplier has simulated by HSPICE using 0.25㎛ n-well CMOS process with a 1.2V supply voltage. Simulation results show that the THD can be 1.28% at maximum differential input of 0.7VP-P.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.1003-1006
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• 2012

The image correction algorithm and system design for CMOS sensor to enhance the image resolution is presented in this paper. The proposed algorithm finds out the image cell from the sensor and process them by the limited memory configuration. The evaluation of the method is done by the designed hardware system. The experimental results are capable of improving contrast per channel and of sensing equalized image quality on an edge of image.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.2
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• pp.106-109
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• 2004

A high-density 3-transistor cell one-time programmable (OTP) ROM array using standard CMOS Gate-Oxide antifuse (AF) is proposed, fabricated, and characterized with $0.18{\mu}m$ CMOS process. The proposed non-volatile high-density OTP ROM is composed of an array of 3-T OTP cells with the 3-T consisting of an nMOS AF, a high voltage (HV) blocking transistor, and a cell access transistor, all compatible with standard CMOS technology.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.5
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• pp.887-895
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• 1987

This paper deals with the CMOS PLA Generator using CHISEL language. The program which plots a CMOS PLA alphanumeric layout automatically according to desired input functions and output functions has been developed. The program consists of procedures. These procedure are drawing a stick diagram with input data, converting any design rule, plotting a physical layout at IBM PC-AT with CIF input data. Physical layout information of dynamic CMOS PLA is stored CIF form. The CMOS PLA Generator is written in CHISEL which is layout language VLSI design tools and run on a VAX11/750 running UNIX.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.12
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• pp.37-42
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• 1997

A new temperature and supply-insensitive CMOS current reference circuit was designed and tested. Te temperature insensuitivity was achieved by eliminating the mobility dependence term through the multiplication of two current components, one which is proportional to mobility and the other which is inversely proportional to mobility, by using a newly designed CMOS square root circuit. The CMOS sqare root circuit was derived from its bipolar counterpart by operating the MOS transistors in the subthreshold region. The supply insensitivity was achieved by using an internal voltage generator. Te test chip was designed ans sent out for fabrication by using a 2.mu.m double-poly double-metal n-well CMOS technology. When an external voltage source was used for the square root circuit, the maximum variation and the average temperature sensitivity were measured to be 3% and 21.4ppm/.deg.C, respectively, for the temperature range of -15~130.deg.C. The maximum current variation with supply voltage was measured to be 3% within the commerical supply voltage range of 4.5~5.5V at 30.deg. C.

• Current Industrial and Technological Trends in Aerospace
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• v.5 no.1
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• pp.56-64
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• 2007

최근들어 오래전부터 컴퓨터의 프로세서와 메모리를 만드는데 사용해 오던 CMOS 공정을 이용하여 이미지 센서를 생산하는 기술이 개발되어 저가격 다량생산과 저전력소모 등의 장점을 무기로 하여 핸드폰카메라와 일반 비디오카메라를 필두로 빠르게 CCD를 대체해나가고 있으며 인공위성의 대표적인 자세측정용 센서인 별센서, 태양센서, 지구센서와 지구관측 또는 우주관측을 위한 영상탑재체에도 빠른 신호처리와 우주환경에서의 높은 내구성으로 인하여 CMOS 이미지센서의 활용이 점차 확대되어 가고 있는 실정이다. 본 논문에서는 먼저 CCD와 CMOS APS 센서의 작동원리와 각각의 장단점을 비교, 분석하고 인공위성 자세결정용 센서인 별센서와 태양센서 및 영상탑재체를 중심으로 한 CMOS APS 센서의 응용사례를 조사, 분석한 결과를 제시하였다.

• Journal of information and communication convergence engineering
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• v.3 no.1
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• pp.28-32
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• 2005

In this paper, we propose a novel test method to effectively detect hard and soft faults in CMOS 2-stage op-amps. The proposed method uses a very high frequency sinusoidal signal that exceeds unit gain bandwidth to maximize the fault effects. Since the proposed test method doesn't require any complex algorithms to generate the test pattern and uses only a single test pattern to detect all target faults, therefore test costs can be much reduced. The area overhead is also very small because the CUT is converted to a unit gain amplifier. Using HSPICE simulation, the results indicated a high degree of fault coverage for hard and soft faults in CMOS 2-stage op-amps. To verify this proposed method, we fabricated a CMOS op-amp that contained various short and open faults through the Hyundai 0.65-um 2-poly 2-metal CMOS process. Experimental results for the fabricated chip have shown that the proposed test method can effectively detect hard and soft faults in CMOS op-amps.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.11-12
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• 2005

2 차원 MEDICI 시뮬레이터를 이용하여 CMOS 회로의 전기적 특성을 조사하였다. CMOS 인버터 회로는 LDMOSFET를 이용하였는데, LDMOSFET에서 전류 및 스위칭 특성에 많은 영향을 주는 곳은 채널이라고 생각되는데, 채널에서의 불순물 농도 변화에 의한 CMOS 회로의 voltage transfer특성, low input voltage($V_{IL}$), high input voltage($V_{IH}$)등을 조사하였다. LDMOSFET에서 N 채널의 농도는 $V_{IL}$에, P 채널의 농도는 $V_{IH}$에 많은 영향을 주었다.

• Journal of the Korean Institute of Intelligent Systems
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• v.16 no.5
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• pp.627-634
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• 2006

We have proposed the methods how to control the slope of CMOS inverter's characteristic and how to shift it in y axis. We control the MOS transistor threshold voltage for these methods. By observing that two transistors are in saturation region at the center of the CMOS inverter's characteristic, we have presented how to make the characteristic for one pole neuron. The circuit level simulation is used for verifying the proposed method. PSpice(OrCAD Co.) is used for circuit level simulation.

• Journal of the Korea Society of Computer and Information
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• v.5 no.3
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• pp.76-83
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• 2000

The continuous time signal system by development of CMOS technology have been receiving consideration attention. In this paper, Low pass filter using new CMOS floating resistor have been designed with cut off frequency for speech signal Processing. Especially a new floating resistor consisting entirely of CMOS devices in saturation has been developed. Linearity within $\pm$0.04% is achieved through nonlinearity via current mirrors over an applied range of $\pm$1V The frequency response exceeds 10MHz, and the resistors are expected to be useful in implementing integrated circuit active RC filters. The low pass filter designed using this method has simpler structure than switched capacitofilter. So reduce the chip area. The characteristics of the designed low pass filter using this method are simulated by pspice program.