• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.9C
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• pp.861-870
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• 2002

In this paper, with targeting on the drawback of RSA of operation speed, a new 1024-bit RSA cryptosystem has been proposed and implemented in hardware to increase the operational speed and perform the variable-length encryption. The proposed cryptosystem mainly consists of the modular exponentiation part and the modular multiplication part. For the modular exponentiation, the RL-binary method, which performs squaring and modular multiplying in parallel, was improved, and then applied. And 4-stage CSA structure and radix-4 booth algorithm were applied to enhance the variable-length operation and reduce the number of partial product in modular multiplication arithmetic. The proposed RSA cryptosystem which can calculate at most 1024 bits at a tittle was mapped into the integrated circuit using the Hynix Phantom Cell Library for Hynix 0.35㎛ 2-Poly 4-Metal CMOS process. Also, the result of software implementation, which had been programmed prior to the hardware research, has been used to verify the operation of the hardware system. The size of the result from the hardware implementation was about 190k gate count and the operational clock frequency was 150㎒. By considering a variable-length of modulus number, the baud rate of the proposed scheme is one and half times faster than the previous works. Therefore, the proposed high speed variable-length RSA cryptosystem should be able to be used in various information security system which requires high speed operation.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.345-345
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• 2012

최근 의료산업에서는 고해상도 및 동영상 구현이 가능한 직접 방식의 X-선 검측센서에서 X-ray 흡수효율이 좋은 반도체 센서(CdTe, CdZnTe 등)와 성숙된 기술, 집적효율이 뛰어난 CMOS 공정을 이용한 제품을 출시하여 대면적화 및 고집적화가 가능하게 되어 응용분야가 점차 확대되고 있는 추세이다. 하지만 이 역시 고 성능의 X-선 동영상 구현을 위해서는 고 해상도 문제, 검출효율 문제, 대면적화의 어려움이 있다. 기존의 X-선 광 도전층의 증착은 증착 속도와 박막 품질에서 우수한 Evaporation 법이 사용되고 있다. 한편, 대면적에 균일한 박막형성이 가능하기 때문에 양산성에서 우월성을 가지는 sputtering법의 경우, 밀도가 높은 소결체 타겟의 제조가 힘들뿐만 아니라 증착 속도가 낮아 장시간 증착 시 낮은 소결밀도로 인한 타겟 Particle 영향으로 인해서 대 면적에 고품질의 박막을 형성하기가 어렵다. 하지만 최근 소결체 타겟 제조기술 발달과 함께, 대면적화와 장시간 증착에 대한 어려움이 해결되고 있어 sputtering 법을 이용한 고품질 박막 제조 기술의 연구가 시급한 실정이다. 본 연구에서는 $50{\times}50$ mm 크기의 non-alkali 유리기판(Corning E2000) 위에 Evaporation과 RF magnetron sputtering을 사용하여 다양한 기판온도 (RT, 100, 200, 300, $350^{\circ}C$)에서 $1{\mu}m$의 두께로 CdTe 박막을 증착하였다. RF magnetron sputtering의 경우 CdTe 단일 타겟(50：50 at%)을 사용하였으며 Base pressure는 약 $5{\times}10^{-6}$ Torr 이하까지 배기하였고, Working pressure는 약 $7.5{\times}10^{-3}$ Torr에서 증착하였다. 시편과 기판 사이의 거리는 70 mm이며 RF 파워는 150 W로 유지하였다. CdTe 박막의 미세구조는 X-ray diffraction (XRD, BRUKER GADDS) 및 Field Emission Scanning Electron Microscopy (FE-SEM, Hitachi)를 사용하여 측정하였다. 또한, 조건별 박막의 조성은 Energy Dispersive X-ray Spectroscopy (EDS, Horiba, 7395-H)을 사용하여 평가하였다. X-선 동영상 장치의 구현을 위해서는 CdTe 다결정 박막의 높은 흡수효율, 전하수집효율 및 SNR (Signal to Noise Ratio) 등의 물성이 요구된다. 이러한 물성을 나타내기 위해서는 CdTe 박막의 높은 결정성이 중요하다. Evaporation과 RF magnetron sputtering로 제작된 CdTe 박막은 공정 온도가 증가함에 따라 기판상에 도달하는 스퍼터 원자의 에너지 증가로 인해서 결정립이 성장한 것을 확인할 수 있었다. 따라서 CdTe 박막이 직접변환방식 고감도 X-ray 검출기 광도 전층 역할을 수행할 수 있을 것으로 기대된다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.19-27
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• 2007

This paper presents power supply-insensitive Gbps low power LVDS I/O circuits. The proposed LVDS I/O has been designed and simulated using 1.8V, $0.18\;{\mu}m$ TSMC CMOS Process. The LVDS I/O includes transmitter and receiver parts. The transmitter circuits consist of a differential phase splitter and an output stage with the switched capacitor common mode feedback(SC-CMFB). The differential phase splitter generates a pair of differential signals which provides a balanced duty $cycle(50{\pm}2%)$ and phase difference$(180{\pm}0.2^{\circ})$ over a wide supply voltage range. Also, $V_{OD}$ voltage is 250 mV which is the smallest value of the permissible $V_{OD}$ range for low power operation. The output buffer maintains the required $V_{CM}$ within the permissible range$(1.2{\pm}0.1V)$ due to the SC-CMFB. The receiver covers a wide input DC offset $range(0.2{\sim}2.6\;V)$ with 38 mV hysteresis and Produces a rail-to-rail output over a wide supply voltage range. Beside, the designed receiver has 38.9 dB gain at 1 GHz, which is higher than conventional receivers.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.11
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• pp.33-40
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• 2005

This paper describes a design of FFT/IFFT Core(FFT256/2k), which is an essential block in terrestrial DMB modem. It has four operation modes including 256/512/1024/2048-point FFT/IFFT in order to support the Eureka-147 transmission modes. The hybrid architecture, which is composed of R2SDF and R2SDC structure, reduces memory by $62\%$ compared to R2SDC structure, and the SQNR performance is improved by TS_CBFP(Two Step Convergent Block Floating Point). Timing simulation results show that it can operate up to 50MHz(a)2.5-V, resulting that a 2048-point FFT/IFFT can be computed in 41-us. The FFT256/2k core designed in Verilog-HDL has about 68,400 gates and 58,130 RAM. The average power consumption estimated using switching activity is about 113-mW, and the total average SQNR of over 50-dB is achieved. The functionality of the core was fully verified by FPGA implementation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.95-101
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• 2009

Random numbers are used in many sorts of applications. Some applications, like simple software simulation tests, communication protocol verifications, cryptography verification and so forth, need various levels of randomness with various process speeds. In this paper, we propose a fast pseudorandom generator module for embedded systems. The generator module is implemented in hardware which can run in two modes, one of which can generate random numbers with higher randomness but which requires six cycles, the other providing its result within one cycle but with less randomness. An ASIP (Application Specific Instruction set Processor) was designed to implement the proposed pseudorandom generator instruction sets. We designed a processor based on the MIPS architecture,, by using LISA, and have run statistical tests passing the sequence of the Diehard test suite. The HDL models of the processor were generated using CoWare's Processor Designer and synthesized into the Dong-bu 0.18um CMOS cell library using the Synopsys Design Compiler. With the proposed pseudorandom generator module, random number generation performance was 239% faster than software model, but the area increased only 2.0% of the proposed ASIP.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.8
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• pp.38-48
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• 2014

In this paper, a design of Signal Processing Analog Front-End IC for Automotive Piezo-Resistive Type Pressure Sensor is presented. In modern society, as the car turns to go from mechanical to electronic technology, the accuracy and reliability of electronic parts required importantly. In order to improve these points, Programmable Gain Amplifier (PGA) amplifies the received signal in accordance with gain for increasing the accuracy after PRT Sensor is operated to change physical pressure signals to electrical signals. The signal amplified from PGA is processed by Digital blocks like ADC, CMC and DAC. After going through this process, it is possible to determine the electrical signal to physical pressure signal. As processing analog signal to digital signal, reliability and accuracy in Analog Front-End IC is increased. The current consumption of IC is 5.32mA. The die area of the fabricated IC is $1.94mm{\times}1.94mm$.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.11
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• pp.56-65
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• 2016

In this paper, in order to reduce the delay and area of the partial product accumulation (PPA) of the parallel decimal multiplier, a tree architecture that composed by multi-operand decimal CSAs and improved CLA is proposed. The proposed tree using multi-operand CSAs reduces the partial product quickly. Since the input range of the recoder of CSA is limited, CSA can get the simplest logic. In addition, using the multi-operand decimal CSAs to add decimal numbers that have limited range in specific locations of the specific architecture can reduce the partial products efficiently. Also, final BCD result can be received faster by improving the logic of the decimal CLA. In order to evaluate the performance of the proposed partial product accumulation, synthesis is implemented by using Design Complier with 180 nm COMS technology library. Synthesis results show the delay of the proposed partial product accumulation is reduced by 15.6% and area is reduced by 16.2% comparing with which uses general method. Also, the total delay and area are still reduced despite the delay and area of the CLA are increased.

• Progress in Medical Physics
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• v.27 no.1
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• pp.1-7
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• 2016

In this work, we considered a compressed-sensing (CS)-based image deblurring scheme with a total-variation (TV) regularization penalty for improving image characteristics in digital tomosynthesis (DTS). We implemented the proposed image deblurring algorithm and performed a systematic simulation to demonstrate its viability. We also performed an experiment by using a table-top setup which consists of an x-ray tube operated at $90kV_p$, 6 mAs and a CMOS-type flat-panel detector having a $198-{\mu}m$ pixel resolution. In the both simulation and experiment, 51 projection images were taken with a tomographic angle range of ${\theta}=60^{\circ}$ and an angle step of ${\Delta}{\theta}=1.2^{\circ}$ and then deblurred by using the proposed deblurring algorithm before performing the common filtered-backprojection (FBP)-based DTS reconstruction. According to our results, the image sharpness of the recovered x-ray images and the reconstructed DTS images were significantly improved and the cross-plane spatial resolution in DTS was also improved by a factor of about 1.4. Thus the proposed deblurring scheme appears to be effective for the blurring problems in both conventional radiography and DTS and is applicable to improve the present image characteristics.

• Journal of the Korean earth science society
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• v.34 no.6
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• pp.588-601
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• 2013

In geophysics and geophysical exploration fields, we can use information about inclination and azimuth in various ways. These include borehole deviation logging for inversion process, real-time data acquisition system, geophysical monitoring system, and so on. This type of information is also necessarily used in the directional drilling of shale gas fields. We thus need to develop a subminiature, low-powered, multi-functional inclination and azimuth measurement system for geophysical exploration fields. In this paper, to develop real-time measurement system, we adopt the high performance low power Micro Control Unit (made with state-of-the-art Complementary Metal Oxide Semiconductor technology) and newly released Micro Electro Mechanical Systems Attitude Heading Reference System sensors. We present test results on the development of a multifunctional real-time inclination and azimuth measurement system. The developed system has an ultra-slim body so as to be installed in 42mm sonde. Also, this system allows us to acquire data in real-time and to easily expand its application by synchronizing with a depth encoder or Differential Global Positioning System.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.410-410
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• 2013

Next-generation nonvolatile memory (NVM) has attracted increasing attention about emerging NVMs such as ferroelectric random access memory, phase-change random access memory, magnetic random access memory and resistance random access memory (RRAM). Previous studies have demonstrated that RRAM is promising because of its excellent properties, including simple structure, high speed and high density integration. Many research groups have reported a lot of metal oxides as resistive materials like TiO2, NiO, SrTiO3 and ZnO [1]. Among them, the ZnO-based film is one of the most promising materials for RRAM because of its good switching characteristics, reliability and high transparency [2]. However, in many studies about ZnO-based RRAMs, there was a problem to get lower current level for reducing the operating power dissipation and improving the device reliability such an endurance and an retention time of memory devices. Thus in this paper, we investigated that highly reproducible bipolar resistive switching characteristics of W doped ZnO RRAM device and it showed low resistive switching current level and large ON/OFF ratio. This may be caused by the interdiffusion of the W atoms in the ZnO film, whch serves as dopants, and leakage current would rise resulting in the lowering of current level [3]. In this work, a ZnO film and W doped ZnO film were fabricated on a Si substrate using RF magnetron sputtering from ZnO and W targets at room temperature with Ar gas ambient, and compared their current levels. Compared with the conventional ZnO-based RRAM, the W doped ZnO ReRAM device shows the reduction of reset current from ~$10^{-6}$ A to ~$10^{-9}$ A and large ON/OFF ratio of ~$10^3$ along with self-rectifying characteristic as shown in Fig. 1. In addition, we observed good endurance of $10^3$ times and retention time of $10^4$ s in the W doped ZnO ReRAM device. With this advantageous characteristics, W doped ZnO thin film device is a promising candidates for CMOS compatible and high-density RRAM devices.