• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.1268-1270
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• 1993

In this study, the characteristics of Si-$SiO_2$ interface and its degradation in short channel SONOSFET nonvolatile memory devices, fabricated by 1Mbit CMOS process($1.2{\mu}m$ design rule), with $65{\AA}$ blocking oxide layer, $205{\AA}$ nitride layer, and $30{\AA}$ tunneling oxide layer on the silicon wafer were investigated using the charge pumping method. For investigating the Si-$SiO_2$ interface characteristics before and after write/erase cycling, charge pumping current characteristics with frequencies, write/erase cycles, as a parameters, were measured. As a result, average Si-$SiO_2$ interface trap density and mean value of capture cross section were determined to be $1.203{\times}10^{11}cm^{-2}eV^{-1}\;and\;2.091{\times}10^{16}cm^2$ before write/erase cycling, respectively. After cycling, when the write/erase cycles are $10^4$, average $Si-SiO_2$ interface trap density was $1.901{\times}10^{11}cm^{-2}eV^{-1}$. Incresing write/erase cycles beyond about $10^4$, Si-$SiO_2$ interface characteristics with write/erase cycles was increased logarithmically.

• Journal of the Korean Vacuum Society
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• v.20 no.3
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• pp.182-188
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• 2011

Polysilazane and polymethylsilazane based precursor films were deposited on Si-substrate by spin-coating, subsequently annealed at $150{\sim}850^{\circ}C$, and characterized. Structural analysis, shrink, compositional change, etch rate, and gap-filling were observed. Annealing the precursor films led to formation of spin-on dielectric films. C-containing precursor films showed that less loss of N, H, and C while less gain of O than that of C-free precursor films at $400^{\circ}C$, but more loss of N, H, and C while more gain of O at $850^{\circ}C$. Thus polysilazane based precursor films exhibited less reduction in thickness of 14.5% than silazane based one of 15.6% at $400^{\circ}C$ but more 37.4% than 19.4% at $850^{\circ}C$. FTIR indicated that C induced smaller amount of Si-O bond, non-uniform property, and lower resistance to chemical etching.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.214.2-214.2
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• 2013

Device performance for the 45 and 32 nm node CMOS technology requires the integration of ultralow-k materials. To lower the dielectric constant for PECVD and spin-on materials, partial replacement of the solid network with air (k=1.01) appears to be more intuitive and direct option. This can be achieved introducting of second "labile" phase during depositoin that is removed during a subsequent UV curing and annealing step. Besides, with shrinking line dimensions the resistivity of barrier films cannot meet the International Technology Roadmap for Semiconductors (ITRS) requirements. To solve this issue self-forming diffusion barriers have drawn attention for great potential technique in meeting all ITRS requirments. In this present work, we report a Cu-V alloy as a materials for the self-forming barrier process. And we investigated diffusion barrier properties of self-formed layer on low-k dielectrics with or without UV curing treatment. Cu alloy films were directly deposited onto low-k dielectrics by co-sputtering, followed by annealing at various temperatures. X-ray diffraction revealed Cu (111), Cu (200) and Cu (220) peaks for both of Cu alloys. The self-formed layers were investigated by transmission electron microscopy. In order to compare barrier properties between V-based interlayer on low-k dielectric with UV curing and interlayer on low-k dielectric without UV curing, thermal stability was measured with various heat treatment temperature. X-ray photoelectron spectroscopy analysis showed that chemical compositions of self-formed layer. The compositions of the V based self-formed barriers after annealing were strongly dominated by the O concentration in the dielectric layers.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2013.10a
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• pp.763-764
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• 2013

A three-dimensional image capturing device and its signal processing algorithm and apparatus are presented. Three dimensional information is one of emerging differentiators that provides consumers with more realistic and immersive experiences in user interface, game, 3D-virtual reality, and 3D display. It has the depth information of a scene together with conventional color image so that full-information of real life that human eyes experience can be captured, recorded and reproduced. 20 Mega-Hertz-switching high speed image shutter device for 3D image capturing and its application to system prototype are presented[1,2]. For 3D image capturing, the system utilizes Time-of-Flight (TOF) principle by means of 20MHz high-speed micro-optical image modulator, so called 'optical resonator'. The high speed image modulation is obtained using the electro-optic operation of the multi-layer stacked structure having diffractive mirrors and optical resonance cavity which maximizes the magnitude of optical modulation[3,4]. The optical resonator is specially designed and fabricated realizing low resistance-capacitance cell structures having small RC-time constant. The optical shutter is positioned in front of a standard high resolution CMOS image sensor and modulates the IR image reflected from the object to capture a depth image (Figure 1). Suggested novel optical resonator enables capturing of a full HD depth image with depth accuracy of mm-scale, which is the largest depth image resolution among the-state-of-the-arts, which have been limited up to VGA. The 3D camera prototype realizes color/depth concurrent sensing optical architecture to capture 14Mp color and full HD depth images, simultaneously (Figure 2,3). The resulting high definition color/depth image and its capturing device have crucial impact on 3D business eco-system in IT industry especially as 3D image sensing means in the fields of 3D camera, gesture recognition, user interface, and 3D display. This paper presents MEMS-based optical resonator design, fabrication, 3D camera system prototype and signal processing algorithms.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.6
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• pp.1056-1063
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• 2008

This paper describes an efficient design of a multi-standard Viterbi decoder that supports multiple constraint lengths and code rates. The Viterbi decoder is parameterized for the code rates 1/2, 1/3 and constraint lengths 7,9, thus it has four operation nodes. In order to achieve low hardware complexity and low power, an efficient architecture based on hardware sharing techniques is devised. Also, the optimization of ACCS (Accumulate-Subtract) circuit for the one-point trace-back algorithm reduces its area by about 35% compared to the full parallel ACCS circuit. The parameterized Viterbi decoder core has 79,818 gates and 25,600 bits memory, and the estimated throughput is about 105 Mbps at 70 MHz clock frequency. Also, the simulation results for BER (Bit Error Rate) performance show that the Viterbi decoder has BER of $10^{-4}$ at $E_b/N_o$ of 3.6 dB when it operates with code rate 1/3 and constraints 7.

• Journal of Radiation Industry
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• v.9 no.1
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• pp.1-7
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• 2015

The trend of x-ray image sensor has been evolved from an amorphous silicon sensor to a crystal silicon sensor. A crystal silicon X-ray sensor, meaning a X-ray CIS (CMOS image sensor), is consisted of three transistors (Trs), i.e., a Reset Transistor, a Source Follower and a Select Transistor, and a photodiode. They are highly sensitive to radiation exposure. As the frequency of exposure to radiation increases, the quality of the imaging device dramatically decreases. The most well known effects of a X-ray CIS due to the radiation damage are increments in the reset voltage and dark currents. In this study, a pixel array of a X-ray CIS was made of $20{\times}20pixels$ and this pixel array was exposed to a high radiation dose. The radiation source was Co-60 and the total radiation dose was increased from 1 to 9 kGy with a step of 1 kGy. We irradiated the small pixel array to get the increments data of the reset voltage and the dark currents. Also, we simulated the radiation effects of the pixel by MCNP (Monte Carlo N-Particle) simulation. From the comparison of actual data and simulation data, the most affected location could be determined and the cause of the increments of the reset voltage and dark current could be found.

• Current Optics and Photonics
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• v.2 no.5
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• pp.422-430
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• 2018

Rolling shutter operation of CMOS cameras can be utilized in optical camera communications in order to transmit data from an LED to mobile devices such as smart-phones. From temporally modulated light, a spatial flicker pattern is obtained in the captured image, and this is used for signal recovery. Due to the degradation of rolling shutter images caused by light smear, motion blur, and focus blur, the conventional decoding schemes for rolling shutter cameras based on the pattern width for 'OFF' and 'ON' cannot guarantee robust communications performance for practical uses. Aside from conventional techniques, such as polynomial fitting, histogram equalization can be used for blurry light mitigation, but it requires additional computation abilities resulting in burdens on mobile devices. This paper proposes a transition-based decoding scheme for rolling shutter cameras in order to offer simple and robust data decoding in the presence of image degradation. Based on the designed synchronization pulse and modulated data symbols according to the LED dimming level, the decoding process is conducted by observing the transition patterns of two sequential symbol pulses. For this, the extended symbol pulse caused by consecutive symbol pulses with the same level determines whether the second pulse should be included for the next bit decoding or not. The proposed method simply identifies the transition patterns of sequential symbol pulses other than the pattern width of 'OFF' and 'ON' for data decoding, and thus, it is simpler and more accurate. Experimental results ensured that the transition-based decoding scheme is robust even in the presence of blurry lights in the captured image at various dimming levels

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.9
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• pp.1158-1165
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• 2021

This paper proposes a CNN accelerator which is optimized Pooling layer operation incorporated in Multiplication And Accumulation(MAC) to reduce the memory size. For optimizing memory and data path circuit, the quantized 8bit integer weights are used instead of 32bit floating-point weights for pre-training of MNIST data set. To reduce chip area, the proposed CNN model is reduced by a convolutional layer, a 4*4 Max Pooling, and two fully connected layers. And all the operations use specific MAC with approximation adders and multipliers. 94% of internal memory size reduction is achieved by simultaneously performing the convolution and the pooling operation in the proposed architecture. The proposed accelerator chip is designed by using TSMC65nmGP CMOS process. That has about half size of our previous paper, 0.8*0.9 = 0.72mm². The presented CNN accelerator chip achieves 94% accuracy and 77us inference time per an MNIST image.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.7
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• pp.822-828
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• 2019

An Augmented Reality(AR) provides virtual information with a real environment, and the processor needs to access the memory for the AR system. However, the processor has the heavy workload as the technology improvement leads to increase the size of data. We need a specific module to reduce the workload to overcome the limitation. In this paper, we propose a Direct Memory Access(DMA) controller displaying image instead of the processor. We implemented the proposed DMA controller on a Field Programmable Gate Array(FPGA) and demonstrated the functionality of the DMA controller based on an Avalon Memory Mapped(Avalon-MM) interface. Also, the DMA controller is fabricated by using Magnachip/Hynix 0.35um CMOS technology and verified the feasibility of the embedded system.

• Journal of IKEEE
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• v.23 no.3
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• pp.917-924
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• 2019

This paper presents a wideband low noise amplifier (LNA) that is suitable for LTE-Advanced and 5G communication standards employing carrier aggregation (CA). The proposed LNA encompasses a common input stage and a dual output second stage with a buffer at each distinct output. This architecture is targeted to operate in both intra-band (contiguous and non-contiguous) and inter-band CA. In the proposed design, the input and second stages employ a gm enhancement with resistive feedback technique to achieve self-biasing, enhanced gain, wide bandwidth as well as reduced noise figure of the proposed LNA. An up/down power controller controls the single input single out (SISO) and single input multiple outputs (SIMO) modes of operation for inter-band and intra-band operations. The proposed LNA is designed with a 45nm CMOS technology. For SISO mode of operation, the LNA operates from 0.52GHz to 4.29GHz with a maximum power gain of 17.77dB, 2.88dB minimum noise figure and input (output) matching performance better than -10dB. For SIMO mode of operation, the proposed LNA operates from 0.52GHz to 4.44GHz with a maximum voltage gain of 18.30dB, a minimum noise figure of 2.82dB with equally good matching performance. An $IIP_3$ value of -6.7dBm is achieved in both SISO and SIMO operations. with a maximum current of 42mA consumed (LNA+buffer in SIMO operation) from a 1.2V supply.