• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.5
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• pp.1104-1109
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• 2015

Due to the rapid growth in digital contents, it is important for us to design a high speed and secure encryption algorithm which is able to comply with the existing and future needs. This paper proposes an alternative approach for self-decimated LM-128 summation sequence generator, which will generate a higher throughput if compared to the conventional generator. We design and implement a threshold clock-controlled LM-128 and prove that it has a lower clock cycle and hence giving a higher key stream generation speed. The proposed threshold clock-control LM-128 generator consists of 256 bits inner state with 128 bits secret key and initialization vector. The cipher achieves a security level of 128 bits to be adapted to the digital contents security with high definition and high quality.

• IEMEK Journal of Embedded Systems and Applications
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• v.16 no.4
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• pp.119-127
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• 2021

The aim of this paper is to propose a less conservative stabilization condition for leader-following sampled-data control of wheeled mobile robot (WMR) systems by using a clock-dependent Lyapunov function (CDLF) with looped functionals. In the leader-following WMR system, the state and input of the leader robot are measured by digital devices mounted on the following robot, and they are utilized to construct the sampled-data controller of the following robot. To design the sampled-data controller, a stabilization condition is derived by using the CDLF with looped functionals, and formulated in terms of sum of squares (SOS). The considered Lyapunov function is a polynomial form with respect to the clock related to the transmitted sampling instants. As the degree of the Lyapunov function increases, the stabilization condition becomes less conservative. This ensures that the designed controller is able to stabilize the system with a larger maximum sampling interval. The simulation results are provided to demonstrate the effectiveness of the proposed method.

• ETRI Journal
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• v.41 no.3
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• pp.383-395
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• 2019

Clock Controlled Dual keeper Domino logic structures (CCDD_1 and CCDD_2) for achieving a high-speed performance with low power consumption and a good noise margin are proposed in this paper. The keeper control circuit comprises an additional PMOS keeper transistor controlled by the clock and foot node voltage. This control mechanism offers abrupt conditional control of the keeper circuit and reduces the contention current, leading to high-speed performance. The keeper transistor arrangement also reduces the loop gain associated with the feedback circuitry. Hence, the circuits offer less delay variability. The design and simulation of various wide fan-in designs using 180 nm CMOS technology validates the proposed CCDD_1 and CCDD_2 designs, offering an increased speed performance of 7.2% and 8.5%, respectively, over a conventional domino logic structure. The noise gain margin analysis proves good robustness of the CCDD structures when compared with a conventional domino logic circuit configuration. A Monte Carlo simulation for 2,000 runs under statistical process variations demonstrates that the proposed CCDD circuits offer a significantly reduced delay variability factor.

• IEIE Transactions on Smart Processing and Computing
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• v.6 no.3
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• pp.220-227
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• 2017

Technology development is leading to the invention of more sophisticated electronics appliances that require long battery life. Therefore, saving power is a major concern in current-day scenarios. A notable source of power dissipation in sequential structures of integrated circuits is due to the continuous switching of high-frequency clock signals, which do not carry any information, and hence, their switching is eliminated by a method called clock gating. In this paper, we have incorporated a recent clock-gating style named Leakage Control Transistor (LECTOR)-based clock gating to drive a multi-stage sequential architectures, and we focus on its performance under three different process corners (fast-fast, slow-slow, typical-typical) through Monte Carlo simulation at 18 GHz clock with 90 nm technology. This gating is found to be one of the best gated approaches for multi-stage architectures in terms of total power consumption.

• BMB Reports
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• v.49 no.11
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• pp.587-589
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• 2016

The circadian clock system enables organisms to anticipate the rhythmic environmental changes and to manifest behavior and physiology at advantageous times of the day. Transcriptional/translational feedback loop (TTFL) is the basic feature of the eukaryotic circadian clock and is based on the rhythmic association of circadian transcriptional activator and repressor. In Drosophila, repression of dCLOCK/CYCLE (dCLK/CYC) mediated transcription by PERIOD (PER) is critical for inducing circadian rhythms of gene expression. Pacemaker neurons in the brain control specific circadian behaviors upon environmental timing cues such as light and temperature cycle. We show that amino acids 657-707 of dCLK are important for the transcriptional activation and the association with PER both in vitro and in vivo. Flies expressing dCLK lacking AA657-707 in $Clk^{out}$ genetic background, homologous to the mouse Clock allele where exon 19 region is deleted, display pacemaker-neuron-dependent perturbation of the molecular clockwork. The molecular rhythms in light-cycle-sensitive pacemaker neurons such as ventral lateral neurons ($LN_vs$) were significantly disrupted, but those in temperature-cycle-sensitive pacemaker neurons such as dorsal neurons (DNs) were robust. Our results suggest that the dCLK-controlled TTFL diversify in a pacemaker-neuron-dependent manner which may contribute to specific functions such as different sensitivities to entraining cues.

• Journal of Communications and Networks
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• v.8 no.1
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• pp.8-12
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• 2006

Master-slave (M-S) strategies implemented with chain circuits are the main option in order to distribute clock signals along synchronous networks in several telecommunication and control applications. Here, we study the two types of masterslave chains: Without clock feedback, i.e., one-way master-slave (OWMS) and with clock feedback, i.e., two-way master-slave (TWMS) considering the slave nodes as second-order phase-locked loops (PLL) for several types of loop low-pass filters.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.38 no.7
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• pp.785-797
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• 2014

Support for the precise time synchronization of EtherCAT, known as distributed clock (DC), enables the design of highly synchronized operations in distributed real-time systems. This study evaluates the performance of the EtherCAT DC through extensive experiments in a real automation system. We constructed an EtherCAT control system using Xenomai and IgH EtherCAT stack, and analyzed the clock deviation for different devices in the network. The results of the evaluation revealed that the accuracy of the synchronized clock is affected by several factors such as the number of slave devices, period of drift compensation, and type of system time base. In particular, we found that careful decision regarding the system time base is required because it has a fundamental effect on the master operation, which results in significantly different performance characteristics.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.12
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• pp.1644-1651
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• 1995

A data and clock recovery integrated circuit for MAC (Multiplexed Analog Component) TV standard is described. The chip performs the recovery of a system clock from a digitally encoded voice signal, clamping of a video signal for DC-level restoration, and precise gain control of a video signal in the presence of a large amplitude variation. A PLL (Phase Locked Loop) is used for timing recovery and a new gain control circuit is proposed which enhances its accuracy and dynamic range by employing two identical four-quadrant analog multipliers. The chip is designed in full custom with 1.5um BiCMOS technology, and layout verification is completed by post-simulation with the extracted circuit.

• The KIPS Transactions:PartA
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• v.19A no.4
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• pp.181-186
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• 2012

The distributed measurement and control system require technology to solve complex synchronization problem among distributed devices. It can be solved by using IEEE Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems to synchronize real-time clocks incorporated within each component of the system. In this paper, we implemented the IEEE 1588v2 PTP emulator on BlueScope BL6000A using a delay request-response mechanism to measure clock synchronization.

• Biomedical Science Letters
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• v.12 no.1
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• pp.53-56
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• 2006

The suprachiasmatic nucleus (SCN) of the anterior hypothalamus is the circadian pacemaker entrained to the 24-hr day by environmental time cues. Major circadian genes such as mPeriod ($mPer1{\sim}3$) and mCryptochrome ($mCry1{\sim}2$) are actively transcribed by the action of CLOCK/BMAL heterodimers, and in turn, these are being suppressed by the mPER/mCRY complex. In the study, the locomotor activity rhythms of mPer1 Knockout (KO) mice are measured, and the expression profiles of Heat Shock Protein 105kDa (HSP 105) genes in the SCN were measured by in situ hybridization. In agreement with previous reports, the locomotor activity rhythm of mPer1 KO mice was much shorter than that of wildtype. In addition, the total bout of activity of mPer1 KO was less in comparison to control mice. The expression of HSP 105 in the SCN of mPer1 KO mice was ranged from CT6 to CT22, with a peak level at CT14, implying that the gene are under the control of circadian clock. However, the expression of HSP 105 in the SCN of wildtype could not be detected in our study. Further analysis will reveal the direct or indirect regulation by mPer1 on the expression in the SCN and the role of the gene in the circadian clock.