• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.71-78
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• 2013

In highly reliable and durable systems, failures due to aging might result in catastrophes. Aging monitoring techniques to prevent catastrophes by predicting such a failure are required. Aging can be monitored by performing a delay test at faster clocks than functional clock in field and checking the current delay state from the test clock frequencies at which the delay test is passed or failed. In this paper, we focus on test clock control scheme for a system-on-chip (SoC) with multiple clock domains. We describe limitations of existing at-speed test clock control methods and present an on-chip faster-than-at-speed test clock control scheme for intra/inter-clock domain test. Experimental results show our simulation results and area analysis. With a simple control scheme, with low area overhead, and without any modification of scan architecture, the proposed method enables faster-than-at-speed test of SoCs with multiple clock domains.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.7
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• pp.624-628
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• 2008

This paper is concerned with multiple motor control using a distributed network control method. Speed and position of multiple motors are synchronized using clock synchronized distributed controllers. CAN (controller area network) is used and a new clock synchronization algorithm is proposed and implemented. To verify the proposed control algorithm, two disks which are attached on two motor shafts are controlled to rotate at the same speed and phase angle with the same time base using network clocks.

• International Journal of Advanced Culture Technology
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• v.4 no.4
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• pp.30-37
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• 2016

In this paper, the method of controlling the clock that is inputted on the hardware from the application, and the hardware design method are to be proposed. When the hardware is synthesized to the Field Programmable Gate Array(FPGA), the input clock is fixed, and when the input clock is changed, the synthesis process must be passed again to require more time. To solve this problem, the Mixed-Mode Clock Manager(MMCM) module is mounted to control the MMCM module from the application. The controlled MMCM module controls the input clock of the module. The experiment was process the Neural Network algorithm in the x86 CPU and SIMT based processor mounted the FPGA. The results of the experiment, SIMT-based processors, the time that is processed at a frequency of 50MHz was 77ms, 100MHz was 34ms. There was no additional synthesis time due to a change of the clock frequency.

• Journal of Institute of Control, Robotics and Systems
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• v.19 no.2
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• pp.125-130
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• 2013

Compared to OWR (One-Way Ranging) method that requires precise network time synchronization, TWR (Two-Way Ranging) method has advantages in building an indoor WPAN (Wireless Personal Area Network) location system with lower cost. However, clock offsets of nodes in WPAN system should be eliminated or compensated to improve location accuracy of the TWR method. Because conventional clock offset elimination methods requires multiple TWR transactions to reduce clock offset, they produce network traffic burden instead. This paper presents a clock offset estimation method that can reduce clock offset error with a single TWR transaction. After relative clock offsets of sensor nodes are estimated, clock offsets of mobile tags are estimated using a single TWR communication. Simulation results show that location accuracy of the proposed method is almost similar to the conventional clock offset elimination method, while its network traffic is about a half of the conventional method.

• Journal of Information Display
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• v.10 no.1
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• pp.37-44
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• 2009

AiPi technology incorporates an embedded clock and control scheme with a point-to-point bus topology, thereby having the smallest possible number of interface lines between a timing controller and column drivers. A point-to-point architecture boosts the data rate and reduces the number of interface lines, because impedance matching can be easily achieved. An embedded clock and control scheme is implemented by means of multi-level signalling, which results in a simple clock/data recovery circuitry. A 46" AiPi-based 10-bit FHD prototype requires only 20 interface lines, compared to 38 lines for mini-LVDS. The measured maximum data rate per data pair is more than 800 Mbps.

• Animal cells and systems
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• v.16 no.1
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• pp.1-10
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• 2012

Most living organisms synchronize their physiological and behavioral activities with the daily changes in the environment using intrinsic time-keeping systems called circadian clocks. In mammals, the key molecular features of the internal clock are transcription- and translational-based negative feedback loops, in which clock-specific transcription factors activate the periodic expression of their own repressors, thereby generating the circadian rhythms. CLOCK and BMAL1, the basic helix-loop-helix (bHLH)/PAS transcription factors, constitute the positive limb of the molecular clock oscillator. Recent investigations have shown that various levels of posttranslational regulation work in concert with CLOCK/BMAL1 in mediating circadian and cellular stimuli to control and reset the circadian rhythmicity. Here we review how the CLOCK and BMAL1 activities are regulated by intracellular distribution, posttranslational modification, and the recruitment of various epigenetic regulators in response to circadian and cellular signaling pathways.

• Molecules and Cells
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• v.39 no.1
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• pp.6-19
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• 2016

Redox signalling comprises the biology of molecular signal transduction mediated by reactive oxygen (or nitrogen) species. By specific and reversible oxidation of redoxsensitive cysteines, many biological processes sense and respond to signals from the intracellular redox environment. Redox signals are therefore important regulators of cellular homeostasis. Recently, it has become apparent that the cellular redox state oscillates in vivo and in vitro, with a period of about one day (circadian). Circadian timekeeping allows cells and organisms to adapt their biology to resonate with the 24-hour cycle of day/night. The importance of this innate biological timekeeping is illustrated by the association of clock disruption with the early onset of several diseases (e.g. type II diabetes, stroke and several forms of cancer). Circadian regulation of cellular redox balance suggests potentially two distinct roles for redox signalling in relation to the cellular clock: one where it is regulated by the clock, and one where it regulates the clock. Here, we introduce the concepts of redox signalling and cellular timekeeping, and then critically appraise the evidence for the reciprocal regulation between cellular redox state and the circadian clock. We conclude there is a substantial body of evidence supporting circadian regulation of cellular redox state, but that it would be premature to conclude that the converse is also true. We therefore propose some approaches that might yield more insight into redox control of cellular timekeeping.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.3
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• pp.506-514
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• 1997

In this paper, we implement digital circuit of despreading delay lock loop for GPS receiver. The designed system consists of Epoch signal generator, two 13bit correlators which correlates the received C/A code and the locally generated C/A code in the receiver, the C/A code generator which generates C/A code of selected satellite, and the direct digital clock synthesizer which generates the clock of the C/A code generator to control the phase and clock rate, the clock controller, and the clock divider. The designed circuit has the function of the acquisition and tracking by the autocorrelation characteristics of Gold code. The controller generates each other control signals according to the correlation value. The designed circuit is simulated to verify the logic functional performance. By using the simulator STR-2770 that generates the virtual GPS signal, the deigned FPGA chip is verified the circuit performance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.139-149
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• 2012

A 3D stacked IC is made by multiple dies (possibly) with heterogeneous process technologies. Therefore, die-to-die variation in 2D chips renders on-package variation (OPV) in a 3D chip. In spite of the different variation effect in 3D chips, generally, 3D die stacking can produce high yield due to the smaller individual die area and the averaging effect of variation on data path. However, 3D clock network can experience unintended huge clock skew due to the different clock propagation routes on multiple stacked dies. In this paper, we analyze the on-package variation effect on 3D clock networks and show the necessity of a post silicon management method such as body biasing technique for the OPV induced 3D clock skew control in 3D stacked IC designs. Then, we present a parametric yield improvement method to mitigate the OPV induced 3D clock skew.

• The Transactions of the Korea Information Processing Society
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• v.6 no.5
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• pp.1351-1361
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• 1999

The wide spread of multimedia system demands a large area viewing display device which can inform a message to many people in open area. This paper is about the design of a large area viewing LED panel control system. The control system runs on 16 bit microprocessor MC68EC000 and has following functions: 16 line clock and time, 2 channel priority interrupt, 2 channel direct memory access, 2 channel 12 bit clock and timer, 2 channel infrared remocon receiver, 2 channel RS-232C with 16 byte FIFO, IBM PC/AT compatible keyboard interface, ISA bus, battery backuped real time clock, battery backuped 256 byte SRAM and watch dog timer. The core circuits are implemented to ASIC, considering lower cost, higher reliability, higher performance, smaller dimension, and lower power consumption. This is verified by simulation and fabricated in 0.6 um CMOS SOG processes. The total gate count is 39,083 and the clock frequency is 48 MGz. The fabricated ASIC is mounted on test board.