• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.11
• /
• pp.1-9
• /
• 1996

In the following paper, new architectural algorithm of clock and data recovery circuit is proposed for 622.08 Mbps optical communication receiver. New algorithm makes use of charge pump PLL using voltage controlled ring oscillator and extracts 8-channel 77.76 MHz clock signals, which are delayed by i/8 (i=1,2, ...8), to convert and recover 8-channel parallel data from 662.08 Mbps MRZ serial data. This circuit includes clock genration block to produce clock signals continuously even if input data doesn't exist. And synchronization of data and clock is doen by the method which compares 1/2 bit delayed onput data and decided dta by extracted clock signals. Thus, we can stabilize frequency and phase of clock signal even if input data is distorted or doesn't exist and simplify receiver architecture compared to traditional receiver's. Also it is possible ot realize clock extraction, data decision and conversion simulataneously. Verification of this algorithm is executed by DESIGN CENTER (version 6.1) using test models which are modelized by analog behavior modeling and digital circuit model, modified to process input frequency sufficiently, in SPICE.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.26 no.12C
• /
• pp.249-254
• /
• 2001

A receiver ASIC for fiber optic modules of STM-1 optical communication has been fabricated with 0.65 $\mu\textrm{m}$ CMOS technology. The ASIC has a limit amplifier circuit for the 155.52 Mbps data reshaping, and a clock extraction circuit for the 155.52 MHz clock recovery. The ASIC has an acquisition aid and LOS monitoring circuit for properly operation with near 155.52 MHz clock frequency in case of the data loss due to transmission line open or data transfer fail. Measured results show that the circuit reshapes data from 5 mV to 1 V wide range of input voltage condition, add it recovers system clock with stable on any condition.

• Korean Journal of Optics and Photonics
• /
• v.16 no.1
• /
• pp.21-26
• /
• 2005

10 GHz clock recovery from 40 Gbit/s optical time-division-multiplexed(OTDM) signal pulses was experimentally demonstrated using an optical phase lock loop based on a terahertz optical asymmetric demultiplexer(TOAD) with a local-reference-oscillator-free electronic feedback circuit. The 10 GHz clock was successfully extracted from 40 Gbit/s signals. The SNR of the time-extracted 10 GHz RF signal to the side components was larger than 40 dB. Also we performed numerical simulation about the extraction process of phase information in TOAD. The lock-in frequency range of the clock recovery is found to be 10 kHz.

• Korean Journal of Optics and Photonics
• /
• v.13 no.4
• /
• pp.295-300
• /
• 2002

We developed an optical transmitter and receiver for an electrical time division multiplexed (ETDM) 20 Gb/s optical transmission system, and experimentally investigated their characteristics. Especially, the clock extraction circuit, which is a key component in realizing broadband optical transmission receivers, was realized by using an NRZ-to-PRZ converter implemented with a half-period delay line and an EX-OR, a high-Q bandpass filter using a cylindrical dielectric resonator, and a microstrip coupled-line bandpass filter. Finally, the bit-error-rate of demultiplexed 10 Gb/s electrical signal after back to-back transmission was measured, and a high receiver sensitivity [-26.2 dBm for NRZ ($2^{7}-1$) pseudorandom binary sequence (PRBS)] was obtained

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.11 no.6
• /
• pp.3208-3229
• /
• 2017

Rectification is an essential procedure for simplifying the disparity extraction of stereo matching algorithms by removing vertical mismatches between left and right images. To support real-time stereo matching, studies have introduced several look-up table (LUT)- and computational logic (CL)-based rectification approaches. However, to support high-resolution images, the LUT-based approach requires considerable memory resources, and the CL-based approach requires numerous hardware resources for its circuit implementation. Thus, this paper proposes a multi-level accumulation-based rectification method as a simple CL-based method and its circuit implementation. The proposed method, which includes distortion correction, reduces addition operations by 29%, and removes multiplication operations by replacing the complex matrix computations and high-degree polynomial calculations of the conventional rectification with simple multi-level accumulations. The proposed rectification circuit can rectify $1,280{\times}720$ stereo images at a frame rate of 135 fps at a clock frequency of 125 MHz. Because the circuit is fully pipelined, it continuously generates a pair of left and right rectified pixels every cycle after 13-cycle latency plus initial image buffering time. Experimental results show that the proposed method requires significantly fewer hardware resources than the conventional method while the differences between the results of the proposed and conventional full rectifications are negligible.

• Journal of Korea Multimedia Society
• /
• v.12 no.3
• /
• pp.329-334
• /
• 2009

When an optical disc is being played. the pick-up converts light to analog signal at first. The analog signal is equalized for removing the inter-symbol interference and then the equalized analog signal is converted into the digital signal for extracting the synchronized data and clock signals. There are a lot of algorithms that minimize the BER in extracting the synchronized data and clock when high. density optical disc like BD is being played in low speed. But if the high-density optical disc is played in high speed, it is difficult to adopt the same extraction algorithm to data PLL and PRML architecture used in low speed application. It is because the signal with more than 800MHz should be processed in those architectures. Generally, in the 0.13-${\mu}m$ CMOS technology, it is necessary to have the high speed analog cores and lots of efforts to layout. In this paper, the parallel data PLL and PRML architecture, which enable to process in BD 8x speed of the maximum speed of the high-density optical disc as the extracting data and clock circuit, is proposed. Test results show that the proposed architecture is well operated without processing error at BD 8x speed.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.24 no.2
• /
• pp.268-275
• /
• 2020

A lightweight hardware design of self-timed ring based true random number generator (TRNG) suitable for information security applications is described. To reduce hardware complexity of TRNG, an entropy extractor with feedback structure was proposed, which minimizes the number of ring stages. The number of ring stages of the FSTR-TRNG was determined to be a multiple of eleven, taking into account operating clock frequency and entropy extraction circuit, and the ratio of tokens to bubbles was determined to operate in evenly-spaced mode. The hardware operation of FSTR-TRNG was verified by FPGA implementation. A set of statistical randomness tests defined by NIST 800-22 were performed by extracting 20 million bits of binary sequences generated by FSTR-TRNG, and all of the fifteen test items were found to meet the criteria. The FSTR-TRNG occupied 46 slices of Spartan-6 FPGA device, and it was implemented with about 2,500 gate equivalents (GEs) when synthesized in 180 nm CMOS standard cell library.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.12C
• /
• pp.1288-1298
• /
• 2002

To implement elliptic curve cryptosystem in GF(2$\^$m/) at high speed, a fast divider is required. Although bit-parallel architecture is well suited for high speed division operations, elliptic curve cryptosystem requires large m(at least 163) to support a sufficient security. In other words, since the bit-parallel architecture has an area complexity of 0(m$\^$m/), it is not suited for this application. In this paper, we propose a new serial-in serial-out systolic array for computing division operations in GF(2$\^$m/) using the standard basis representation. Based on a modified version of tile binary extended greatest common divisor algorithm, we obtain a new data dependence graph and design an efficient bit-serial systolic divider. The proposed divider has 0(m) time complexity and 0(m) area complexity. If input data come in continuously, the proposed divider can produce division results at a rate of one per m clock cycles, after an initial delay of 5m-2 cycles. Analysis shows that the proposed divider provides a significant reduction in both chip area and computational delay time compared to previously proposed systolic dividers with the same I/O format. Since the proposed divider can perform division operations at high speed with the reduced chip area, it is well suited for division circuit of elliptic curve cryptosystem. Furthermore, since the proposed architecture does not restrict the choice of irreducible polynomial, and has a unidirectional data flow and regularity, it provides a high flexibility and scalability with respect to the field size m.