• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.13 no.2
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• pp.59-65
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• 2013

Microprocessors of 8 to 16 bits have become the first step of today's computer development with excellent capability and a lot of those are still used in the educational spots. In this study, execution times of Intel series microprocessors(${\mu}ps$) available to microprocessor systems of 8 to 32 bits are obtained and compared by I/O programs. The compared result showed that execution time related to the instruction cycles of 8 bit 8051 was longer than that of 8 bit 8051 and of 16 bit 8086 by a lot of number of clocks in cases of clock frequencies at 4 MHz and at 12 MHz. In cases of really many using ${\mu}p$ clock frequencies, it showed that execution times of instructions have become faster by the order of 8085, 8086, 8051 and 80386. It can be helped to interface with ${\mu}ps$ for real time control through comparing with execution times of I/O programs by mainly many usable Intel series ${\mu}ps$ in our nation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.1
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• pp.109-116
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• 2018

This paper describes an area-efficient design of SHA-256 hash function that is widely used in various security protocols including digital signature, authentication code, key generation. The SHA-256 hash processor includes a padder block for padding and parsing input message, so that it can operate without software for preprocessing. Round function was designed with a 16-bit data-path that processed 64 round computations in 128 clock cycles, resulting in an optimized area per throughput (APT) performance as well as small area implementation. The SHA-256 hash processor was verified by FPGA implementation using Virtex5 device, and it was estimated that the throughput was 337 Mbps at maximum clock frequency of 116 MHz. The synthesis for ASIC implementation using a $0.18-{\mu}m$ CMOS cell library shows that it has 13,251 gate equivalents (GEs) and it can operate up to 200 MHz clock frequency.

• Journal of Photoscience
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• v.9 no.2
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• pp.9-12
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• 2002

Circadian rhythms can be seen in a variety of physiological functions in insects. Light is a powerful zeitgeber not only synchronizing but also modulating the rhythm to adjust insect's temporal structure to seasonal changes in the environmental cycle. There are two general effects of the length of light phase within 24 hr light cycles on the circadian rhythms, i.e., the modulation of free-running period and the waveform. Since the photoperiodic modulation of the free-running period is induced even in the clock mutant flies, per$\^$s/, the free-running period is not fully determined genetically. In crickets, the ratio of activity (a) and rest phase (p) under the constant darkness (DD) is clearly dependent on the photoperiod under which they have been kept. When experienced the longer photoperiod it becomes smaller. The magnitude of change in a/p-ratio is dependent on the number of cycles they experienced. The neuronal activity of the optic lobe in DD shows the a/p-ratio changing with the preceding photoperiod. These data suggest that a single circadian pacemaker stores and maintains the photoperiodic information and that there is a system that accumulates the effects of single photoperiod to cause greater effects.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.31-39
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• 1998

This paper presents the design and implementation of a new multimedia fixed-point DSP (MDSP) core for portable multimedia applications. The MDSP instruction set is designed through the analysis of multimedia algorithms and DSP instruction sets. The MDSP architecture employs parallel processing techniques, such as SIMD and vector processing as well as DSP techniques. The instruction set can handle various data formats and MDSP can perform two MAC operations in parallel. The switching network and packing network can increase the performance by overlapping data rearrangement cycles with computation cycles. We have designed Verilog HDL models and the 0.6 $\mu\textrm{m}$ Samsung KG75000 SOG library is used. The total gate count is 68,831 and the clock frequency is 30 MHz.

• ETRI Journal
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• v.31 no.6
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• pp.784-794
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• 2009

We present a full HD (1080p) H.264/AVC High Profile hardware encoder based on fast motion estimation (ME). Most processing cycles are occupied with ME and use external memory access to fetch samples, which degrades the performance of the encoder. A novel approach to fast ME which uses shared multibank memory can solve these problems. The proposed pixel subsampling ME algorithm is suitable for fast motion vector searches for high-quality resolution images. The proposed algorithm achieves an 87.5% reduction of computational complexity compared with the full search algorithm in the JM reference software, while sustaining the video quality without any conspicuous PSNR loss. The usage amount of shared multibank memory between the coarse ME and fine ME blocks is 93.6%, which saves external memory access cycles and speeds up ME. It is feasible to perform the algorithm at a 270 MHz clock speed for 30 frame/s real-time full HD encoding. Its total gate count is 872k, and internal SRAM size is 41.8 kB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.3
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• pp.21-29
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• 2012

This paper presents optimized searching technique to improve the performance of H.264/AVC. By using the proposed forward and backward searching algorithm, redundant cycles of latency for data reordering can be removed. Furthermore, in order to reduce the total number of execution cycles of CAVLC encoder, early termination mode and two stage pipelined architecture are proposed. The experimental result shows that the proposed architecture needs only 36.0 cycles on average for each $16{\times}16$ macroblock encoding. The proposed architecture improves the performance by 57.8% than that of previous designs. The proposed CAVLC encoder was implemented using Verilog HDL and synthesized with Magnachip $0.18{\mu}m$ standard cell library. The synthesis result shows that the gate count is about 17K with 125Mhz clock frequency.

• ETRI Journal
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• v.27 no.5
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• pp.511-524
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• 2005

In this paper, we propose a novel hardware architecture for an intra-prediction, integer transform, quantization, inverse integer transform, inverse quantization, and mode decision module for the macroblock engine of a new video coding standard, H.264. To reduce the cycle of intra prediction, transform/quantization, and inverse quantization/inverse transform of H.264, a reduction method for cycle overhead in the case of I16MB mode is proposed. This method can process one macroblock for 927 cycles for all cases of macroblock type by processing $4{\times}4$ Hadamard transform and quantization during $16{\times}16$ prediction. This module was designed using Verilog Hardware Description Language (HDL) and operates with a 54 MHz clock using the Hynix $0.35 {\mu}m$ TLM (triple layer metal) library.

• ETRI Journal
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• v.30 no.1
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• pp.167-169
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• 2008

In this paper, we propose hardware architecture for a high-speed context-adaptive variable length coding (CAVLC) decoder in H.264. In the CAVLC decoder, the codeword length of the current decoding block is used to determine the next input bitstreams (valid bits). Since the computation of valid bits increases the total processing time of CAVLC, we propose two techniques to reduce processing time: one is to reduce the number of decoding steps by introducing a lookup table, and the other is to reduce cycles for calculating the valid bits. The proposed CAVLC decoder can decode $1920{\times}1088$ 30 fps video in real time at a 30.8 MHz clock.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.451-454
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• 2004

The reconfigurable architecture is increasingly important for design of multi-mode communication systems and computation-intensive DSP systems. The proposed coarse-grain architecture is based on a reconfigurable processing element consisting of a MAC unit, a register file, a context data register, and PE interconnect control blocks. The main feature of the Proposed architecture is the loop context which enables faster configuration. Also, we propose another area-efficient reconfigurable architecture with improved reconfigurability. The SystemC modeling results show that the proposed architecture can reduce 9 clock cycles of 2D DCT compared to existing architectures.

• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.2
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• pp.79-84
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• 2012

Efficient arithmetic design is essential to implement error correcting codes and cryptographic applications over finite fields. This article presents an efficient $AB^2$ multiplier in GF($2^m$) using a polynomial representation. The proposed multiplier produces the result in m clock cycles with a propagation delay of two AND gates and two XOR gates using O($2^m$) area-time complexity. The proposed multiplier is highly modular, and consists of regular blocks of AND and XOR logic gates. Especially, exponentiation, inversion, and division are more efficiently implemented by applying $AB^2$ multiplication repeatedly rather than AB multiplication. As compared to related works, the proposed multiplier has lower area-time complexity, computational delay, and execution time and is well suited to VLSI implementation.