• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.282-285
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• 2002

In this paper, we designed of low power system by using dynamic scaling. As an effective low-power design, dynamic voltage/frequency scaling recently has received a lot of attention. In dynamic frequency scheme, all execution cycles are driven by the clock frequency that switched frequency dynamically at run time. The algorithm schedules lower frequency operators at earlier steps and higher frequency operators to later steps. This algorithm assigned the frequency for each execution cycle then it adjusted the voltage associated with the frequency.

• Journal of the korean Society of Automotive Engineers
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• v.10 no.3
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• pp.45-50
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• 1988

The measurement system of the pressure in engine cylinder is developed with the aids of the microcomputer, A/D converter and simple electrical circuits. The experiment is performed in 4 cycle single cylinder Gasoline engine. When data for the pressure progress is sampled, clock signal or signal from the crank angle is used as trigger. The variation of the pressure during the cycles can be well obtained experimentally. So, the informations which are necessary in the combustion analysis, i.e. expansion pressure, indicated mean effective pressure, the magnitude and time of the maximum pressure ignition time, the rate of pressure rise and heat release and combustion rates can be obtained by the calculation using experimental data. Also, the informations about the after-burning process, the existence of the detonation waves and end time of combustion can be investigated from this study.

• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2534-2536
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• 2002

This paper presents the design of high speed bit and word processor for sequence logic control using a FPGA. This FPGA is able to execute sequence instruction during program fetch cycle, because the program memory was separated from the data memory for high speed execution at 40MHz clock. Also this processor has 274 instructions set with a 32bit fixed width, so instruction decoding time and data memory interface time was reduced. This FPGA was synthesized by V600EHQ240 and Foundation tool of Xilinx company. The final simulation was successfully performed under Foundation tool simulation environment. And the FPGA programmed by VHDL for a 240 pin HQFP package. Finally the benchmark was performed to prove that the designed for bit and word processor has better performance than Q4A of Mitsubishi for the sequence logic control.

• Journal of Institute of Control, Robotics and Systems
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• v.22 no.8
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• pp.643-649
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• 2016

This paper presents a new image cache algorithm for real-time implementation of high-resolution color image warping. The cache memory is divided into four cache memory modules for simultaneous readout of four input image pixels in consideration of the color filter array (CFA) pattern of an image sensor and CFA image warping. In addition, a pipeline structure from the cache memory to an interpolator is shown to guarantee the generation of an output image pixel at each system clock cycle. The proposed image cache algorithm is applied to an FPGA-based real-time color image warping, and experimental results are presented to show the validity of the proposed method.

• ETRI Journal
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• v.34 no.2
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• pp.284-287
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• 2012

Quantum-dot cellular automata (QCA) is one of the few alternative computing platforms that has the potential to be a promising technology because of higher speed, smaller size, and lower power consumption in comparison with CMOS technology. This letter proposes an optimized full comparator for implementation in QCA. The proposed design is compared with previous works in terms of complexity, area, and delay. In comparison with the best previous full comparator, our design has 64% and 85% improvement in cell count and area, respectively. Also, it is implemented with only one clock cycle. The obtained results show that our full comparator is more efficient in terms of cell count, complexity, area, and delay compared to the previous designs. Therefore, this structure can be simply used in designing QCA-based circuits.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.11
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• pp.17-26
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• 1993

In this paper, a VlSI architecture for Reed-Solomon (RS) decoder based on the Berlekamp algorithm is proposed. The proposed decoder provided both erasure and error correcting capability. In order to reduc the chip area, we reformulate the Berlekamp algorithm. The proposed algorithm possesses a recursive structure so that the number of cells for computing the errata locator polynomial can be reduced. Moreover, in our approach, only one finite field multiplication per clock cycle is required for implementation, provided an improvement in the decoding speed, and the overall architecture features parallel and pipelined structure, making a real time decoding possible. From the performance evaluation, it is concluded that the proposed VLSI architecture is more efficient in terms of VLSI implementation than the rcursive architecture based on the Euclid algorithm.

• Journal of the Korea Society for Simulation
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• v.12 no.1
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• pp.73-83
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• 2003

This paper presents armed vehicle BAttle Group Simulation model(called BAGSim) which is an object-oriented simulation system for representing battle group engagement consisting of tanks and helicopters. BAGSim is designed in the evolutionary software life cycle approach with the Unified Software Development Process, and implemented with C++ language. BAGSim consists of a preprocessor for engagement scenario definition and simulation data set up, a main processor for triggering engagement event and advancing simulation clock, and a post processor to record simulation histories. Application scenario covers several type of engagement among command tanks, fight tanks, scout helicopters, attack helicopters, anti-tank guided missiles, and decoys. Thus, BAGSim can be effectively used as an analytic tool to examine some operational concepts and tactics, further experimentally fine tune tank design options.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.52 no.2
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• pp.85-90
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• 2003

This paper has presented the efficient implementation of MPEG-4 simple profile video decoder, which is used as video compression standard in mobile video communication. We have used the ARM9 processor in implementing this MPEG-4 simple profile, which requires much processing power and low power implementation. At first we implemented with C-language under the PC environment with ADS(ARM Developer Suite) environment, and then we have tried to reduce a clock cycle for a power consumption optimization through conversion an assembly language for C-code partly. We have verified the processor is operated at 22.47MHz operation after optimization, but 148MHz before optimization.

• Journal of Embryo Transfer
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• v.24 no.4
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• pp.237-247
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• 2009

Melatonin (N-acetyl-5-methoxytryptamine) is the major neurohormone secreted during the night by the vertebrate pineal gland. The circadian pattern of pineal melatonin secretion is related to the biological clock within the suprachiasmatic nucleus (SCN) of the hypothalamus in mammals. The SCN coordinates the body's rhythms to the environmental light-dark cycle in response to light perceived by the retina, which acts mainly on retinal ganglion cells that contain the photopigment melanopsin. Calbindin-D9k (CaBP-9k) is a member of the S100 family of intracellular calcium- binding proteins, and in this review, we discuss the involvement of melatonin and CaBP-9k with respect to calcium homeostasis and apoptotic cell death. In future studies, we hope to provide important information on the roles played by CaBP-9k in cell signal transduction, cell proliferation, and $Ca^{2+}$ homeostasis in vivo and in vitro.

• Journal of Electrical Engineering and information Science
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• v.1 no.1
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• pp.118-128
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• 1996

In safety critical hard real-time systems, a timing fault may yield catastrophic results. In order to eliminate the timing faults from the fast responsive real-time control systems, it is necessary to schedule a code based on high precision timing analysis. Further, the schedulability enhancement by having multiple processors is of wide spread interest. However, although an instruction level parallel processing is quite effective to improve the schedulability of such a system, none of the real-time applications employ instruction level parallel scheduling techniques because most of the real-time scheduling models have not been designed for fine-grain execution. In this paper, we present a timing constraint model specifying high precision timing constraints, and a practical approach for constructing static schedules for a VLIW execution model. The new model and analysis can guarantee timing accuracy to within a single machine clock cycle.