• Applied Microscopy
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• v.34 no.1
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• pp.51-59
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• 2004

The high acceleration voltage system used in scanning electron microscope were designed and manufactured to test its stability. The Cockcroft-Walton circuits are used both in the cathode voltage up to -30 kV and in the Wehnelt cylinder of -2 kV. The operating voltage of 6 V was applied to the heating of the filament. The wave forms which are formed in the second leg of the high voltage transformer were observed in the oscilloscope with 2 V of DC input. When the high voltages were in the range between 5 kV and 12 kV, the highest value of the stabilities of the generated voltages was obtained as 0.002%.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.12
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• pp.63-72
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• 2007

This paper addresses the system development that can transfer data and TDM signals simultaneously by adding TDM pseudowires functions to E-PON system. E-PON technology is one of many technologies which can realize FTTH, has raised as next generation access network solution having both low-cost Ethernet technology and optical infrastructure. TDM pseudowires service is the new voice/data conversion technology which can transfer the existing TDM circuit switched voice and data over packet switching network. In this paper, this system can provide both data and TDM service without deteriorating QoS by adding TDM pseudowires service module to E-PON, and then implementing QoS control function. Therefore, the competitive system which can transfer both data and TDM signal, can be installed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.1A
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• pp.134-141
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• 2007

This paper presents a frequency synthesizer(FS) for 5.2GHz/2.4GHz dual band wireless applications which is designed in a standard $0.18{\mu}m$ CMOS1P6M process. The 2.4GHz frequency is obtained from the 5.2GHz output frequency of Voltage Controlled Oscillator (VCO) by using the Switched Capacitor (SC) and the divider-by-2. Power dissipations of the proposed FS and VCO are 25mW and 3.6mW, respectively. The tuning range of VCO is 700MHz and the locking time is $4{\mu}s$. The simulated phase noise of PLL is -101.36dBc/Hz at 200kHz offset frequency from 5.0GHz with SCA circuit on.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.8-16
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for column-parallel analog-to-digital converter (ADC) array used in a low noise CMOS image sensor. The proposed modulator implements two switched capacitor integrators and a single-bit comparator within only 10-㎛ column-pitch for column-parallel ADC array. Also, peripheral circuits for driving all column modulators include a non-overlapping clock generator and a bias circuit. The proposed delta-sigma modulator has been implemented in a 110-nm CMOS process. It achieves 88.1-dB signal-to-noise-and-distortion ratio (SNDR), 88.6-dB spurious-free dynamic range (SFDR), and 14.3-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 418 for 12-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 970×10 ㎛2 and 248 ㎼, respectively.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.9
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• pp.4177-4185
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• 2012

LEDs are becoming the most suitable candidate replacing traditional fluorescent lamps because of its eco-friendly characteristics. LEDs are also actively used to design green building system and to make outdoor billboard as a back-light system due to its high energy efficiency. In this paper, we have developed AC direct driver for $12{\times}12$ FLB(flexible LED board) and LED flat light without SMPS. It has LID-PC-R101B driver IC that can support the high power factor and be composed of LED switching circuit in group. Also, an elaborate system designs can guarantee a high luminous efficiency, a high reliability and a low power consumption. The proposed FLB has the ultra slim shape of $450{\times}450$ mm, width of 4 mm and weight of 280 g. In the end, we have developed a prototype of FLB for billboard and flat light for room lighting with AC direct driver iposrder to verify the performance of the proposed system.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.1 s.307
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• pp.45-52
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• 2006

In this paper, authors propose a step-up converter of pulse width modulation (PWM) and power factor correction (PFC) by using a novel loss-less snubber. The proposed converter for a discontinuous conduction mode (DCM) eliminates the complicated circuit control requirement and reduces the size of components. The input current waveform in the proposed converter is got to be a sinusoidal form of discontinuous pulse in proportion to magnitude of ac input voltage under the constant duty cycle switching. Thereupon, the input power factor is nearly unity and the control method is simple. In the general DCM converters, the switching devices are fumed-on with the zero current switching (ZCS), and the switching devices must be switched-off at a maximum reactor current. To achieve a soft switching (ZCS and ZVS) of the switching turn-off, the proposed converter is constructed by using a new loss-less snubber which is operated with a partial resonant circuit. The result is that the switching loss is very low and the efficiency of converter is high. Some simulative results on computer and experimental results are included to confirm the validity of the analytical results.

• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.278-284
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• 1998

This paper describes a l0b CMOS A/D converter (ADC) for HDTV applications. The proposed ADC adopts a typical multi-step pipelined architecture. The proposed circuit design techniques are as fo1lows: A selective channel-length adjustment technique for a bias circuit minimizes the mismatch of the bias current due to the short channel effect by supply voltage variations. A power reduction technique for a high-speed two-stage operational amplifier decreases the power consumption of amplifiers with wide bandwidths by turning on and off bias currents in the suggested sequence. A typical capacitor scaling technique optimizes the chip area and power dissipation of the ADC. The proposed ADC is designed and fabricated in s 0.8 um double-poly double-metal n-well CMOS technology. The measured differential and integral nonlinearities of the prototype ADC show less than ${\pm}0.6LSB\;and\;{\pm}2.0LSB$, respectively. The typical ADC power consumption is 119 mW at 3 V with a 40 MHz sampling rate, and 320 mW at 5 V with a 50 MHz sampling rate.

• The Magazine of the IEIE
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• v.25 no.6
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• pp.69-78
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• 1998

프레임 릴레이망을 백본으로 한 LAN과 LAN접속으로 형성되는 기업통신망이 현재 활발히 전개되면서 인터넷을 통한 광고, 전자거래가 중요한 서비스로 진행되고 있다. 국내의 프레임 릴레이 서비스 현황을 살펴보면 KT, 데이콤, 일부기업등에서 프레임 릴레이 교환기를 수입하여 주고객인 기업에 서비스를 제공하고 있다. 이들은 사용자 요구에 의해 주로 LAN과 LAN에 접속된 라우터 등의 종단 시스템간 PVC(영구가상회선: Permanant Virtual Circuit)접속을 통하여 다양한 서비스를 제공하면서 독자적인 기업통신체계를 구축하고 있는 실정이다. 이와같이 사용자 요구로 PVC등록시 프레임 릴레이망과 LAN을 연결하는 링크의 QoS(서비스 질: Quality of Service), 트래픽 파라메터는 수동적으로 설정된다. 현재 국내에서는 프레임 릴레이 교환기 개발은 전무하고 단지 그들을 수입하여 운용하는 수준이며 향후 ATM(비동기 전달모드: Asynchronous Transfer Mode)망의 중요 서비스 연동이 될 프레임 릴레이 기술은 심도있게 연구되고 있다. 향후 고속통신을 제공하는 백본망은 기존의 프레임 릴레이망과 ATM망이 공존할 추세이며 점진적으로 프레임 릴레이망은 사라질 것이다. 이때 ATM 망이 기존의 프레임 릴레이망을 백본으로 한 기업통신망 수용시 원할한 서비스 제공을 위해서는 프레임 릴레이망을 백본으로 채택한 기존의 기업통신망을 ATM망에서 수용시 야기되는 문제점의 제시와 이의 해결은 매우 중요하다고 생각된다. FR/ATM(Frame Relay/ATM)연동시 기업통신망 입장에서는 PVC뿐만 아니라 SVC(교환가상회선: Switched Virtual Circuit)호처리가 수용되어야 한다. 이와같이 PVC와 SVC 수용으로 기업통신망은 통신망의 구성 및 관리가 복잡, 다양해지며, 또 그 기업은 관련된 다양하고 수많은 고객과 접속될 수 있어야 한다. 이때 ATM망을 백본으로 한 공중망이 관련 기업의 사설 정보를 관리하도록 한다는 것은 그 서비스의 이용자에게 보안문제를 제기함은 물론 서비스 이용자가 자신의 망에서 동작하는 여러 서비스를 고객 스스로가 관리하는 것이 바람직하다. CNN(고객망관리 : Customer Network Management)은 이러한 고객에 의한 통신망, 공중망에 대한 부분적 관리 및 서비스에 대한 관리가 이루어 질수 있도록 수행하는 기능이다. 본 논문에서는 ATM망이나 프레임 릴레이망과 ATM 망이 공존시 기업통신망관점에서 야기되는 문제점의 제시와 이의 해결 방안을 살펴보았다. 우선 FR/ATM 연동에서 PVC설정뿐만 아니라 SVC 설정 방법의 연구, 이때 고려된 QoS,트래픽 처리과정을 살펴보았다. 또한 망관리 입장에서 기업통신망 관리자와 ATM망 관리자와의 온-라인 서비스를 제공하기 위해서는 변화된 통신망 차원서의 확장된 Managed Object(MO)를 근간으로한 체계적인 CNN-NMS(CNM-Network management System)연동을 살펴본후 결론에서는 추후 계속연구 및 조사 되어야 할 항목을 기업통신망 입장에서 서술하여 보았다.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.3
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• pp.184-196
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for precision measurement of current flowing through a secondary cell battery in a battery management system (BMS). The proposed modulator implements two switched capacitor integrators and a single-bit comparator with peripheral circuits such as a non-overlapping clock generator and a bias circuit. The proposed structure is designed to be applied to low-side current sensing method with low common mode input voltage. Using the low-side current measurement method has the advantage of reducing the burden on the circuit design. In addition, the ±30mV input voltage is resolved by the ADC with 15-bit resolution, eliminating the need for an additional programmable gain amplifier (PGA). The proposed a single-bit 2nd-order delta-sigma modulator has been implemented in a 350-nm CMOS process. It achieves 95.46-dB signal-to-noise-and-distortion ratio (SNDR), 96.01-dB spurious-free dynamic range (SFDR), and 15.56-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 400 for 5-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 670×490 ㎛2 and 414 ㎼, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.17-26
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• 2016

This work proposes a 12b 60MS/s 0.18um CMOS Flash-SAR ADC for various systems such as wireless communications and portable video processing systems. The proposed Flash-SAR ADC alleviates the weakness of a conventional SAR ADC that the operation speed proportionally increases with a resolution by deciding upper 4bits first with a high-speed flash ADC before deciding lower 9bits with a low-power SAR ADC. The proposed ADC removes a sampling-time mismatch by using the C-R DAC in the SAR ADC as the combined sampling network instead of a T/H circuit which restricts a high speed operation. An interpolation technique implemented in the flash ADC halves the required number of pre-amplifiers, while a switched-bias power reduction scheme minimizes the power consumption of the flash ADC during the SAR operation. The TSPC based D-flip flop in the SAR logic for high-speed operation reduces the propagation delay by 55% and the required number of transistors by half compared to the conventional static D-flip flop. The prototype ADC in a 0.18um CMOS demonstrates a measured DNL and INL within 1.33LSB and 1.90LSB, with a maximum SNDR and SFDR of 58.27dB and 69.29dB at 60MS/s, respectively. The ADC occupies an active die area of $0.54mm^2$ and consumes 5.4mW at a 1.8V supply.