• Journal of the Institute of Convergence Signal Processing
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• v.2 no.4
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• pp.97-102
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• 2001

In computer-aided design, partitioning is task of clustering objects into groups to that a given objection function is optimized It is used at the layout level to fin strongly connected components that can be placed together in order to minimize the layout area and propagation delay. Partitioning can also be used to cluster variables and operation into groups for scheduling and unit selection in high-level synthesis. The most popular algorithms partitioning include the Kernighan-Lin algorithm Fiduccia-Mattheyses heuristic and simulated annealing In this paper we propose a genetic algorithm searching solution space for the circuit partitioning problem. and then compare it with simulated annealing by analyzing the results of implementation.

• The Journal of the Korea Contents Association
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• v.21 no.7
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• pp.164-170
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• 2021

In VLSI design, partitioning is a task of clustering objects into groups so that a given objective circuit is optimized. It is used at the layout level to find strongly connected components that can be placed together in order to minimize the layout area and propagation delay. The most popular algorithms for partitioning include the Kernighan-Lin algorithm, Fiduccia-Mattheyses heuristic and simulated annealing. In this paper, we propose a adapted genetic algorithm searching solution space for the circuit partitioning problem, and then compare it with simulated annealing and genetic algorithm by analyzing the results of implementation. As a result, it was found that an adaptive genetic algorithm approaches the optimal solution more effectively than the simulated annealing and genetic algorithm.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.3
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• pp.535-540
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• 1987

This paper proposes a circuit partitioning method and a multifunctional BILBO which can perform the multimodule test in the case of testing VLSI circuits. By using these circuit partitioning method and multifunctional BILBO, test time and cost can be reduced greatly by performing the pipeline test method. And the quantity of circuit that shold be added for testing is also reduced in half by interposing only one BILBO between each module. Also, we confirmed that the multifunctional BILBO proposed here has high error detection capability by analyzing error detection capability of this multifunctional BILBO in mathematics.

• ETRI Journal
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• v.24 no.6
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• pp.473-476
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• 2002

This letter proposes an efficient kernel-based partitioning algorithm for reducing area and power dissipation in combinational circuit designs using don't-care sets. The proposed algorithm decreases power dissipation by partitioning a given circuit using a kernel extracted from the logic. The proposed algorithm also reduces the area overhead by minimizing duplicated gates in the partitioned sub-circuits. The partitioned subcircuits are further optimized utilizing observability don't-care sets. Experimental results for the MCNC benchmarks show that the proposed algorithm synthesizes circuits that on the average consume 22.5% less power and have 12.7% less area than circuits generated by previous algorithms based on a precomputation scheme.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.6
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• pp.1-8
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• 1999

In circuit partitioning problem, work on vertex ordering have used to get good results for k-way partitioning. Body of work constructs a partitioning by first consturcting a vertex ordering, then splitting it. We present a re-placement algorithm for enhanced results by replacing and splitting the cllusters repeatedly. Experimental results on several circuits show that our approach achieves enhancement.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.823-826
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• 2003

FPGA-based logic emulator with lane gate capacity generally comprises a large number of FPGAs connected in mesh or crossbar topology. However, gate utilization of FPGAs and speed of emulation are limited by the number of signal pins among FPGAs and the interconnection architecture of the logic emulator. The time-multiplexing of interconnection wires is required for multi-FPGA system incorporating several state-of-the-art FPGAs. This paper proposes a circuit partitioning algorithm called SCATOMi(SCheduling driven Algorithm for TOMi)for multi-FPGA system incorporating four to eight FPGAs where FPGAs are interconnected through TOMi(Time-multiplexed, Off-chip, Multicasting interconnection). SCATOMi improves the performance of TOMi architecture by limiting the number of inter-FPGA signal transfers on the critical path and considering the scheduling of inter-FPGA signal transfers. The performance of the partitioning result of SCATOMi is 5.5 times faster than traditional partitioning algorithms. Architecture comparison show that the pin count is reduced to 15.2%-81.3% while the critical path delay is reduced to 46.1%-67.6% compared to traditional architectures.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.4
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• pp.1-10
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• 1998

Partitioning problem of large combinational logic has been studied in real world. Most of logic include undectable faults from the structure of it's redundant, fan-out-reconvergent, and symetrical feature. BPT algorithm is proposed to enhance the fault voverage for combinational logic partitioning. This algorithm partitions the logic by cut the lines related to undetectable structure when seperating. Controllability and observability are considered in the process of partitioning. This algorithm is evaluated effective by testing ISCAS85 circuits.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.529-532
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• 1988

This paper proposes a graph matching algorithm based on simulated annealing, which assures the globally optimal solution for circuit partitioning for the placement in the rectilinear region occurring as a result of the pre-placement of some macro cells, or onto the nonplanar surface in some military or space applications. The circuit graph ($G_{C}$) denoting the circuit topology is formed by a hierarchical bottom-up clustering of cells, while another graph called region graph ($G_{R}$) represents the geometry of a planar rectilinear region or a nonplanar surface for circuit placement. Finding the optimal many-to-one vertex mapping function from $G_{C}$ to $G_{R}$, such that the total mismatch cost between two graphs is minimal, is a combinatorial optimization problem which was solved in this work for various examples using simulated annealing.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8B
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• pp.1477-1486
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• 2000

This paper proposes an efficient kernel-based partitioning algorithm for reducing area and power dissipation in combinational circuit design.. The proposed algorithm decreases the power consumption by partitioning a given circuit utilizing a kernel, and reduces the area overhead by minimizing duplicated gates in the partitioned subcircuits. Experimental results for the MCNC benchmarks show that the proposed algorithm is effective by generating circuits consuming 43.6% less power with 30.7% less area on the average, when compared to the previous algorithm based on precomputation circuit structure.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.4
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• pp.85-92
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• 1995

A new partitioning algorithm has been developed to implement a large circuit by using multiple field programmable gate array (FPGA) chips. While the conventional partitioning is to minimze the number of nets cut under size constraints, partitioning for multiple FPGAs has several additional constraints so that each partitioned subcircuit can be implemented in a FPGA chip. To obtain satisfactory results under the constraints, the partitioning is performed in two steps whhich are the intial partitioning for global optimization and the iterative partitioning improvements for constraint satisfaction. Experismental results using the MCNC benchmark examples show that our partition method produces better results thatn those of other recent approaches on the average.