• 한국통신학회논문지
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• 제25권6B호
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• pp.1114-1119
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• 2000

In this paper, a current comparative frequency automatic tuning circuit for the CMOS bandpass filter are designed with the new architecture. And also, when the designed circuit is compared the typical tuning circuit, it has very simple architecture that is composed of the current comparator and charge pump and operated in 2V power supply. The proposed tuning circuit automatically compensate the difference between the operating current of the integrator and the reference current which is specified. Using CMOS 0.25um parameter, a CMOS bandpass active filter with center frequency(fo=100MHz) is designed, and according to the transister size the variation of the center frequency is simulated. As the HSPICE simulation results, the tuning operating of the proposed current comparative frequency automatic tuning circuit is verified.

• Journal of Power Electronics
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• 제8권2호
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• pp.148-155
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• 2008

In this paper, a cost-effective PDP driving circuit using the transformer network is proposed. Compared with the previous works, the half-bridge type energy recovery circuit recovers the reactive energy not to the capacitor but to the source. A single sustain board architecture removes the blocking switches which are placed on the discharge path in parallel, thus reducing the number of devices. A simple reset circuit generates the same waveforms as the previous approaches. The circuit configuration and modified driving waveforms are compared with the previous works. The validity of the proposed simplified driver is verified through tests using a 6-inch panel.

• 정보처리학회논문지A
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• 제18A권2호
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• pp.39-44
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• 2011

본 논문은 통합 비디오 코덱에 적용할 수 있는 DCT와 양자화 회로에 대한 고성능 구조를 제안한다. 제안된 구조는 JPEG, MPEG-1/2/4, H.264, VC-1과 같은 동영상 압축 표준들에 사용되는 모든 변환과 양자화에 적용할 수 있다. 통합 DCT 회로 구조를 위해 8x8 DCT의 변환행렬을 재배치하는 순열행렬을 정의하였고 $4{\times}4$ DCT의 변환행렬과 통합하기 위해 $8{\times}8$ 변환행렬을 4개의 $4{\times}4$ 변환행렬로 나누었다. $8{\times}8$ DCT는 재배치와 분할된 변환행렬을 기반으로 $4{\times}4$ DCT 연산을 반복하여 수행된다. 구현된 회로는 사용자가 변환 계수를 입력하기 때문에 앞으로 등장할 어떤 종류의 DCT 변환에도 매우 쉽게 확장할 수 있다. DCT 회로의 곱셈기들은 회로 크기를 최소화하기 위해 양자화 회로에서 사용되는 곱셈기들과 공유하였다. 이때, 양자화 회로는 회로 구현에 필요한 자원과 처리 시간의 증가 없이 DCT 회로와 통합된다. 제안된 DCT와 양자화 회로는 RTL로 구현하였고 FPGA가 탑재된 보드에서 동작을 검증하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권3호
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• pp.356-363
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• 2014

In this paper, we propose a new memristor-based crossbar array architecture, where a single memristor array and constant-term circuit are used to represent both plus-polarity and minus-polarity matrices. This is different from the previous crossbar array architecture which has two memristor arrays to represent plus-polarity and minus-polarity connection matrices, respectively. The proposed crossbar architecture is tested and verified to have the same performance with the previous crossbar architecture for applications of character recognition. For areal density, however, the proposed crossbar architecture is twice better than the previous architecture, because only single memristor array is used instead of two crossbar arrays. Moreover, the power consumption of the proposed architecture can be smaller by 48% than the previous one because the number of memristors in the proposed crossbar architecture is reduced to half compared to the previous crossbar architecture. From the high areal density and high energy efficiency, we can know that this newly proposed crossbar array architecture is very suitable to various applications of analog neuromorphic computing that demand high areal density and low energy consumption.

• Journal of Information Processing Systems
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• 제5권4호
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• pp.187-196
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• 2009

This paper presents compact cryptographic hardware architecture suitable for the Mobile Trusted Module (MTM) that requires low-area and low-power characteristics. The built-in cryptographic engine in the MTM is one of the most important circuit blocks and contributes to the performance of the whole platform because it is used as the key primitive supporting digital signature, platform integrity and command authentication. Unlike personal computers, mobile platforms have very stringent limitations with respect to available power, physical circuit area, and cost. Therefore special architecture and design methods for a compact cryptographic hardware module are required. The proposed cryptographic hardware has a chip area of 38K gates for RSA and 12.4K gates for unified SHA-1 and SHA-256 respectively on a 0.25um CMOS process. The current consumption of the proposed cryptographic hardware consumes at most 3.96mA for RSA and 2.16mA for SHA computations under the 25MHz.

• 전기전자학회논문지
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• 제18권2호
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• pp.228-233
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• 2014

In this paper, we propose a CMOS-memristor hybrid circuit that can perform 4-bit multiplication for future energy-efficient computing in nano-scale digital systems. The proposed CMOS-memristor hybrid circuit is based on the parallel architecture with AND and OR planes. This parallel architecture can be very useful in improving the power-delay product of the proposed circuit compared to the conventional CMOS array multiplier. Particularly, from the SPECTRE simulation of the proposed hybrid circuit with 0.13-mm CMOS devices and memristors, this proposed multiplier is estimated to have better power-delay product by 48% compared to the conventional CMOS array multiplier. In addition to this improvement in energy efficiency, this 4-bit multiplier circuit can occupy smaller area than the conventional array multiplier, because each cross-point memristor can be made only as small as $4F^2$.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.1355-1360
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• 2005

In this paper, we approach the problem of image filter design automation using a kind of intrinsic evolvable hardware architecture. For the purpose of implementing the intrinsic evolution process in a common FPGA chip and evolving a complicated digital circuit system-image filter, the design automation system employs the reconfigurable circuit architecture as the reconfigurable component of the EHW. The reconfigurable circuit architecture is inspired by the Cartesian Genetic Programming and the functional level evolution. To increase the speed of the hardware evolution, the whole evolvable hardware system which consists of evolution algorithm unit, fitness value calculation unit and reconfigurable unit are implemented by a commercial FPGA chip. The Celoxica RC1000 card which is fitted with a Xilinx Virtex xcv2000E FPGA chip is employed as the experiment platform. As the result, we conclude the terms of the synthesis report of the image filter design automation system and hardware evolution speed in the Celoxica RC1000 card. The evolved image filter is also compared with the conventional image filter form the point of filtered image quality.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.125-128
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• 2001

In this paper, we propose a low power Scan-based Built-ln Self Test based on circuit partitioning and pattern suppression using modified test control unit. To partition a CUT(Circuit Under Testing), the MHPA(Multilevel Hypergraph Partition Algorithm) is used. As a result of circuit partition, we can reduce the total length of test pattern, so that power consumptions are decreased in test mode. Also, proposed Scan-based BIST architecture suppresses a redundant test pattern by inserting an additional decoder in BIST control unit. A decoder detects test pattern with high fault coverage, and applies it to partitioned circuits. Experimental result on the ISCAS benchmark circuits shows the efficiency of proposed low power BIST architecture.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.II
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• pp.854-857
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• 2005

We developed new circuit architecture for reducing the power consumption and chip-size of driver ICs. In this paper we describe a new drive scheme, based on the concept of time -sharing output and optimal circuit design based on color resolution. In case of 132 x 176-pixel class, we used only 8 O p-A mps for a 262-k color display.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권4호
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• pp.477-483
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• 2015

The k-Winners-Take-All (kWTA) is an operation to find the largest k (>1) inputs among N inputs. Parallel search algorithm of kWTA for digital inputs is not invented yet, so most of digital kWTA architectures have O(N) time complexity. A parallel search algorithm for digital kWTA operation and the circuits for its VLSI implementation are presented in this paper. The proposed kWTA architecture can compare all inputs simultaneously in parallel. The time complexity of the new architecture is O(logN), so that it is scalable to a large number of digital data. The high-speed kWTA operation and its O(logN) dependency of the new architecture are verified by simulations. It takes 290 ns in searching for 5 winners among 1024 of 32 bit data, which is more than thousands of times faster than existing digital kWTA circuits, as well as existing analog kWTA circuits.