• ETRI Journal
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• v.39 no.5
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• pp.746-755
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• 2017

In this paper, an electrostatic discharge (ESD) protection circuit is designed for use as a 12 V power clamp by using a parasitic-diode-triggered silicon controlled rectifier. The breakdown voltage and trigger voltage ($V_t$) of the proposed ESD protection circuit are improved by varying the length between the n-well and the p-well, and by adding $n^+/p^+$ floating regions. Moreover, the holding voltage ($V_h$) is improved by using segmented technology. The proposed circuit was fabricated using a $0.18-{\mu}m$ bipolar-CMOS-DMOS process with a width of $100{\mu}m$. The electrical characteristics and robustness of the proposed ESD circuit were analyzed using transmission line pulse measurements and an ESD pulse generator. The electrical characteristics of the proposed circuit were also analyzed at high temperature (300 K to 500 K) to verify thermal performance. After optimization, the $V_t$ of the proposed circuit increased from 14 V to 27.8 V, and $V_h$ increased from 5.3 V to 13.6 V. The proposed circuit exhibited good robustness characteristics, enduring human-body-model surges at 7.4 kV and machine-model surges at 450 V.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.24 no.8 s.179
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• pp.1885-1898
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• 2000

Welding quality is closely related to the arc state. So, it is very important to estimate the arc state in real time. In the short circuit transfer region of CO2 are welding, the spatter , as it is well known, is mainly generated on an instance of short circuit or on an instance that the are is ignited after short circuit, or on the cases of an instantaneous short circuit. If the short circuit period or the arc time is irregular, the spatter is generated more than it is regular. Thus there is a close relationship of the amount of the spatter generation with the arc stability. In this paper, to develop the index for estimating the arc stability in short circuit transfer range Of CO2 arc welding, the welding current and are voltage waveforms were measured and the spatter generated was captured and measured. The correlation analysis of the measured amount of the spatter with the factors (the components and the standard deviations of the components) was performed, and the factors that have a considerable influence on the spatter generation among all factors were selected. And some cases of models consisted of the factors were presented, and a mathematical index model which can make an estimation the amount of the spatter from these models with multiple regression analysis. Also, it was compared how much the amount of the spatter generated under the selected welding conditions do these index models fit, and the index model to estimate the arc stability which represent the spatter generation most appropriately was developed

• Transactions of the Korean Society of Mechanical Engineers A
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• v.26 no.8
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• pp.1552-1564
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• 2002

Meter-in, meter-out and bleed-off circuits are widely utilized in order to adjust the speed of a hydraulic actuator by using a flow control valve and in order to regulate the pressure of a hydraulic volume by using a simple on-off valve. In these circuits, a relief valve serves either to maintain constant system pressure or to protect the system from over-pressure loading. The relief valve of a bleed-off circuit is the second case frequently undergoing on-off action during operation. It makes the analysis of the pressure control characteristics of the circuit highly difficult. In this paper, steady-state flow rate, pressure, heat loss and efficiency of the three circuits are reexamined and basic experiments far obtaining the characteristics of a pump and relief valve are conducted. Finally, simple empirical first-order dynamic models of decreasing and increasing pressure were separately proposed and verified by comparison with experiment. As the result, the basis for the theoretical analysis of the pressure control characteristics of a bleed-off circuit using a simple on-off valve is established.

• Journal of the Korean Society for Precision Engineering
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• v.18 no.6
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• pp.93-101
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• 2001

This paper presents modeling of an inductive micro position sensing system and its analysis. The parameters affected the system response are excitation frequency, turn ratio, input position, air-gap size, load resistance, and geometric dimensions. To analyze the system, we try to establish a modeling based on an equivalent magnetic circuit with permeances. The model is verified by the experimental results from 1 kHz to 20 kHz. The magnetic circuit model is well fitted to the experimental data except a little error due to LC resonance in the large turn-ratio system. Modeling enables us to theoretically approach the response characteristics. Based on the magnetic circuit model, system parameters can be selected in such a way to obtain the required characteristics such as high sensitivity, good linearity, or small size.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.9
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• pp.4159-4164
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• 2012

This paper presents a chaotic circuit with voltage controllability for secure communication applications. The proposed circuit which has two control voltages consists of the nonlinear function block(NFB) with three MOS transistors, one source follower and non-overlapping two-phase clock generator for sample and hold. By SPICE simulation, chaotic dynamics such as time waveform, frequency analysis and bifurcations were analyzed. SPICE results showed that proposed circuit can make various chaotic signals by control voltage.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.8
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• pp.3976-3982
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• 2013

This paper presents a temperature analysis of the chaotic behavior in the voltage controlled CMOS chaotic circuit. The circuit is based on a simple nonlinear function block which is needed for chaotic signal generation. It consists of a NFB (nonlinear function block), a level shifter and non-overlapping two-phase clock for sample and hold. By SPICE simulation, chaotic dynamics such as frequency spectra and bifurcations according to the temperature variations were analyzed. And, it was showed that the circuit can generate discrete chaotic signals within control voltage in the range from 1.2 V to 2.3 V in a specific temperature condition of $25^{\circ}C$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.9
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• pp.875-880
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• 2011

We design and analyze the cloaking circuit using 2D transmission line structure to make up for the weakness of the established cloaking circuit using only lumped inductor and capacitor elements. The 2D transmission line structure enables one to conveniently design the cloaking circuit with available element values. All the necessary analysis and synthesis(design) formulas have been derived. A cloaking circuit for a cylindrical scatterer in free space has been designed based on the provided design formulas and its effects have been investigated using the circuit simulator ADS. The effect of the cloaking medium for this specific case has been observed to be about 10.5 dB.

• Progress in Superconductivity and Cryogenics
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• v.6 no.2
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• pp.25-28
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• 2004

Three-phase inductive superconducting fault current limiter (SFCL) with DC reactor rated on 6.6 $KV_{rms}/200 A_{rms}$ has been developed in Korea. This system consists of one DC reactor, AC/DC power converter, and a three-phase transformer, which is called magnetic core reactor (MCR). This paper deals with the short-circuit analysis of the SFCL. The DC reactor was the HTS solenoid coil whose inductance was 84mH. The power converter was performed as the dual-mode operation for dividing voltage between the rectifying devices. The short-term normal operation (1 see) and short-circuit tests (2∼3 cycles) of this SFCL were performed successfully. In regular short-circuit test, the fault current was limited as 30% of rated short-circuit current at 2 cycles after the fault. The experimental results have a very similar tendency to the simulation results. Using the technique for the fault detection and SCR firing control, the fault current limiting rate of the SFCL was improved. From this research, the parameters for design and manufacture of large-scale SFCL were obtained.

• Progress in Superconductivity and Cryogenics
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• v.14 no.3
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• pp.43-47
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• 2012

A linear compressor generates pulsating pressure and oscillating flow in a cryocooler such as Stirling cryocooler and pulse tube refrigerator. It is driven by AC power source and designed to operate at resonance of piston motion. The driving voltage level is determined by electric parameters of resistance, inductance and thrust constant of linear motor. From voltage equation on linear motor, the power factor of driving power is inherently less than 1. The phase difference between voltage and current of supplied power can be zero using capacitor and this can minimize a supply voltage level. Especially, the linear compressor of kW class requires high voltage and thus can cause a difficulty in selecting power supply unit due to limitation of voltage level. The capacitor in driving electric circuit is useful to settle this problem. In this study, the electric circuit of linear compressor is analytically investigated with assumption of mechanical resonance. The electric parameters of commercial linear motor are used in the analysis. The effects of capacitor on driving voltage level and power factor are investigated. From analytic results, it is shown that the voltage level can be mimized with using capacitor in driving electric circuit.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.4
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• pp.243-250
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• 2005

Test methodology is diversity by devices and the number of test pattern is tremendous because the digital circuit includes TTL and CMOS family ICs as well as high density devices such as ROM and RAM. Accordingly, the quick and effective test strategy is required to enhance the test productivity. This paper proposes the test strategy which is able to be applied efficiently to the diversity devices on the digital circuit board by analyzing the structure and characteristic of the digital device. Especially, this test strategy detects the faulted digital device or the faulted digital circuit on the digital board using SSA(Serial Signature Analysis) technique based on the polynomial division theory The SSA technique identifies the faults by comparing the reminder from good device with reminder from the tested device. At this time, the reminder is obtained by enforcing the data stream obtained from output pins of the tested device on the LFSR(Linear Feedback Shift Register) representing the characteristic equation. Also, the method to obtain the optimal signature analysis circuit is explained by furnishing the short bit input streams to the long bit input streams to the LFSR having 8, 12, 16, 20bit input/output pins and by analyzing the occurring probability of error which is impossible to detect. Finally, the effectiveness of the proposed test strategy is verified by simulating the stuck at 1 errors or stuck at 0 errors for several devices on typical 8051 digital board.