• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.4
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• pp.276-281
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• 2010

A 2.5 V feed-forward second-order deltasigma modulator for audio application is presented. A 9-level quantizer with a tree-structured dynamic element matching (DEM) was employed to improve the linearity by shaping the distortion resulted from the capacitor mismatch of the feedback digital-toanalog converter (DAC). A chopper stabilization technique (CHS) is used to reduce the flicker noise in the first integrator. The prototype delta-sigma analogto-digital converter (ADC) implemented in a 65 nm 1P8M CMOS process occupies 0.747 $mm^2$ and achieves 109.1 dB dynamic range (DR), 85.4 dB signal-to-noise ratio (SNR) in a 24 kHz audio signal bandwidth, while consuming 14.75 mW from a 2.5 V supply.

• Journal of IKEEE
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• v.18 no.1
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• pp.119-127
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• 2014

This paper presents a CMOS readout circuit for MEMS(Micro Electro Mechanical System) acceleration sensors. It consists of a MEMS accelerometer, a capacitance to voltage converter(CVC) and a second-order switched-capacitor ${\Sigma}{\Delta}$ modulator. Correlated-double-sampling(CDS) and chopper-stabilization(CHS) techniques are used in the CVC and ${\Sigma}{\Delta}$ modulator to reduce the low-frequency noise and DC offset. The sensitivity of the designed CVC is 150mV/g and its non-linearity is 0.15%. The duty cycle of the designed ${\Sigma}{\Delta}$ modulator output increases about 10% when the input voltage amplitude increases by 100mV, and the modulator's non-linearity is 0.45%. The total sensitivity is 150mV/g and the power consumption is 5.6mW. The proposed circuit is designed in a 0.35um CMOS process with a supply voltage of 3.3V and a operating frequency of 2MHz. The size of the designed chip including PADs is $0.96mm{\times}0.85mm$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.221-224
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• 2012

This paper presents a CMOS interface circuit for MEMS acceleration sensor. It consists of a capacitance to voltage converter(CVC), a second-order switched-capacitor (SC) integrator and comparator. A bandgap reference(BGR) has been designed to supply a stable bias to the circuit and a ${\Sigma}{\Delta}$ Modulator with chopper - stabilization(CHS) has also been designed for more suppression of the low frequency noise and offset. As a result, the output of this ${\Sigma}{\Delta}$ Modulator increases about 10% duty cycle when the input voltage amplitude increases 100mV and the sensitivity is x, y-axis 0.45v/g, z-axis 0.28V/g. This work is designed and implemented in a 0.35um CMOS technology with a supply voltage of 3.3V and a sampling frequency of 3MHz sampling frequency. The size of the designed chip including PADs is $0.96mm{\times}0.85mm$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.569-572
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• 2014

This paper presents a CMOS switched-capacitor interface circuit for MEMS capacitive sensors. It consist of a capacitance to voltage converter(CVC), a second-order ${\Sigma}{\Delta}$ modulator, and a comparator. A bias circuit is also designed to supply constant bias voltages and currents. This circuit employes the correlated-double-sampling(CDS) and chopper-stabilization(CHS) techniques to reduce low-frequency noise and offset. The designed CVC has a sensitivity of 20.53mV/fF and linearity errors less than 0.036%. The duty cycle of the designed ${\Sigma}{\Delta}$ modulator output increases about 5% as the input voltage amplitude increases by 100mV. The designed interface circuit shows linearity errors less than 0.13%, and the current consumption is 0.73mA. The proposed circuit is designed in a 0.35um CMOS process with a supply voltage of 3.3V. The size of the designed chip including PADs is $1117um{\times}983um$.

• ETRI Journal
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• v.33 no.6
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• pp.897-903
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• 2011

A hybrid ${\Delta}{\Sigma}$ modulator for audio applications is presented in this paper. The pulse generator for digital-to-analog converter alleviates the requirement of the external clock jitter and calibrates the coefficient variation due to a process shift and temperature changes. The input resistor network in the first integrator offers a gain control function in a dB-linear fashion. Also, careful chopper stabilization implementation using return-to-zero scheme in the first continuous-time integrator minimizes both the influence of flicker noise and inflow noise due to chopping. The chip is implemented in a 0.13 ${\mu}m$ CMOS technology (I/O devices) and occupies an active area of 0.37 $mm^2$. The ${\Delta}{\Sigma}$ modulator achieves a dynamic range (A-weighted) of 97.8 dB and a peak signal-to-noise-plus-distortion ratio of 90.0 dB over an audio bandwidth of 20 kHz with a 4.4 mW power consumption from 3.3 V. Also, the gain of the modulator is controlled from -9.5 dB to 8.5 dB, and the performance of the modulator is maintained up to 5 nsRMS external clock jitter.