• ETRI Journal
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• 제38권6호
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• pp.1240-1249
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• 2016

With the number of IP cores in a multicore system-on-chip increasing to up to tens or hundreds, the role of on-chip interconnection networks is vital. We propose a networks-on-chip-style bus network as a compromise and redefine the exploration problem to find the best IP tiling patterns and communication path combinations. Before solving the problem, we estimate the time complexity and validate the infeasibility of the solution. To reduce the time complexity, we propose two fast exploration algorithms and develop a program to implement these algorithms. The program is executed for several experiments, and the exploration time is reduced to approximately 1/22 and 7/1,200 at the first and second steps of the exploration process, respectively. However, as a trade-off for the time saving, the time cost (TC) of the searched architecture is increased to up to 4.7% and 11.2%, respectively, at each step compared with that of the architecture obtained through full-case exploration. The reduction ratio can be decreased to 1/4,000 by simultaneously applying both the algorithms even though the resulting TC is increased to up to 13.1% when compared with that obtained through full-case exploration.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.785-788
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• 2005

In this study, micro-scale, high-performance, solenoid-type RF chip inductors were investigated. The size of the RF chip inductors fabricated in this work was $1.0{\times}0.5{\times}0.5mm^3$ The material and shape of the core were 96% $Al_2O_3$ and I-type. The material and number of turn of coil were copper (Cu) and 6. The diameter ($40{\mu}m$) of coil and length (0.35mm) of solenoid were determined by a Maxwell three-dimensional field simulator to maximize the performance of the inductors. High frequency characteristics of the inductance (L) and quality-factor (Q) of developed inductors were measured using an RF Impedance/Material Analyzer (HP4291B with HP16193A test fixture). The inductors developed have inductances of 10.8nH and quality factors of 25.2 at 250MHz, and show results comparable to those measured for the inductors prepared by CoilCraftTm that is one of the best chip inductor company in the world. The simulated data predicted the high-frequency data of the Land Q of the inductors developed well.

• 한국통신학회논문지
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• 제35권2A호
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• pp.128-133
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• 2010

본 논문에서는 나카가미 페이딩 채널 환경에서 전력 혹은 전송률 적응화 된 직접 대역확산 부호분할 다중접속 통신시스템에서의 최적 칩률에 관하여 연구한다. 주파수 효율을 최대화하는 최적의 칩률은 다중경로 세기 프로파일과 직접파 성분, 그리고 적응화 방식에 의해 결정됨을 알았다. 전송률 적응화 방식에서의 최적의 칩률은 채널 파라미터에 상관없이 다중경로 지연 확산 $1/T_m$ 보다 적다. 이 결과는 전송률 적응화 방식에서는 상관 수신기가 RAKE 수신기보다 더 높은 주파수 효율을 얻을 수 있다는 것을 의미한다. 반면에 전송 전력 적응화 방식에서는 최적의 칩률과 그에 상응하는 RAKE 수신기의 탭 수가 다중경로 세기 프로파일과 직접파 성분에 관한 함수임을 알 수 있었다.

• 전기학회논문지
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• 제61권2호
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• pp.347-353
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• 2012

In this paper, authors will develop the quick and precise remote controller of automatic fire detection equipment (P-type one-class receiver) based on information communication technology (IT). The remote controller detects the fire and disaster in the building automatically and quickly and then activates the facilities to extinguish the fire and disaster, monitoring such situation in a real time through wire-wireless communication network. The proposed remote controller is applied a programmable logic device (PLD) micom. of one-chip type which is small size and lightweight and also has highly sensitive-precise reliabilities. The one-chip type PLD micom. analyzes digital signals from sensors, then activates fire extinguishing facilities for alarm and rapid suppression in a case of fire and disaster. The detected data is also transferred to a remote situation room through wire-wireless network of RS232c and bluetooth communication, and then the situation room sends an emergency alarm signal. The automatic fire detection equipment (AFDE) based on IT will minimize the life and wealth loss while prevents fire and disaster.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권3호
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• pp.359-366
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• 2016

Today's multi-core technology rapidly increases with more and more Intellectual Property cores on a single chip. Network-on-Chip (NoC) is an emerging communication network design for SoC. For efficient on-chip communication, routing algorithms plays an important role. This paper proposes a novel multicast routing technique entitled as Docket NoC (Dt-NoC), which eliminates the need of routing tables for faster communication. This technique reduces the latency and computing power of NoC. This work uses a CURVE restriction based algorithm to restrict few CURVES during the communication between source and destination and it prevents the network from deadlock and livelock. Performance evaluation is done by utilizing cycle accurate RTL simulator and by Cadence TSMC 18 nm technology. Experimental results show that the Dt-NoC architecture consumes power approximately 33.75% 27.65% and 24.85% less than Baseline XY, EnA, OEnA architectures respectively. Dt-NoC performs good as compared to other routing algorithms such as baseline XY, EnA, OEnA distributed architecture in terms of latency, power and throughput.

• 전자공학회논문지C
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• 제35C권2호
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• pp.29-35
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• 1998

This paper describes architectures and design of a SIMD type parallel image processing chip called SliM-II. The chiphas a linear array of 64 processing elements (PEs), operates at 30 MHz in the worst case simulation and gives at least 1.92 GIPS. In contrast to existing array processors, such as IMAP, MGAP-2, VIP, etc., each PE has a multiplier that is quite effective for convolution, template matching, etc. The instruction set can execute an ALU operation, data I/O, and inter-PE communication simulataneously in a single instruction cycle. In addition, during the ALU/multiplier operation, SliM-II provides parallel move between the register file and on-chip memory as in DSP chips, SliM-II can greatly reduce the inter-PE communication overhead, due to the idea a sliding, which is a technique of overlapping inter-PE communication with computation. Moreover, the bandwidth of data I/O and inter-PE communication increases due to bit-parallel data paths. We used the COMPASS$^{TM}$ 3.3 V 0.6.$\mu$m standrd cell library (v8r4.10). The total number of transistors is about 1.5 muillions, the core size is 13.2 * 13.0 mm$^{2}$ and the package type is 208 pin PQ2 (Power Quad 2). The performance evaluation shows that, compared to a existing array processors, a proposed architeture gives a significant improvement for algorithms requiring multiplications.s.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(5)
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• pp.171-174
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• 2000

In stead of RF module which has been used conventionally in many remote measurement applications, a new type of remote measurement system based on PCS(Personal communication system) and one chip Microcontroller is proposed in this work. PCS has many advantages with respect to cost reliability, communication quality, and so on. The proposed system consists of three different modules: PCS module, micro-controller module, and sensor module. System configuration as well as illustrative experiments will be described in detail.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제9권8호
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• pp.3103-3120
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• 2015

This paper presents a single-phase energy metering chip with built-in calibration function to measure electric power quantities. The entire chip consists of an analog front end, a filter block, a computation engine, a calibration engine, and an external interface block. The key design issues are how to reduce the implementation costs of the computation engine from repeatedly used arithmetic operations and how to simplify calibration procedure and reduce calibration time. The proposed energy metering chip simplifies the computation engine using time-division multiplexed arithmetic units. It also provides a simple and fast calibration scheme by using integrated digital calibration functionality. The chip is fabricated with 0.18-μm six-layer metal CMOS process and housed in a 32-pin quad-flat no-leads (QFN) package. It operates at a clock speed of 4096 kHz and consumes 9.84 mW in 3.3 V supply.

• ETRI Journal
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• 제31권2호
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• pp.111-120
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• 2009

Network-on-chip (NoC) architecture provides a highper-formance communication infrastructure for system-on-chip designs. Circuit-switched networks guarantee transmission latency and throughput; hence, they are suitable for NoC architecture with real-time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication circuits, and allocates a proper bandwidth for each circuit. Simulation results show that the average waiting times of packets in a switch in $6{\times}6$6, $8{\times}8$, and $10{\times}10$ mesh NoC networks are 0.59, 0.62, and 0.61, respectively. The latency of circuits is significantly decreased. Furthermore, the buffer of a switch in NoC only needs to accommodate the data of one time slot. The cost of the switch in the circuit-switched network can be reduced using our scheme. Our design provides an effective solution for a critical step in NoC design.

• 한국인터넷방송통신학회논문지
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• 제22권6호
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• pp.43-49
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• 2022

FMCW레이다는 일반 차량의 충돌방지용도 뿐만 아니라 자율주행시스템에서 활발히 센서로서 사용이 되고 있다. 본 논문에서는 자율주행센서로서 개발한 2-chip 기반의 FMCW MIMO(Multi Input Multi Output) 레이다 설계 및 구현에 대해서 설명하였다. 사용 칩을 이용하여 48채널의 가상배열을 이용하여 방위각 해상도가 우수하게 설계하였으며, 특히 Frame 기반과 Chirp 기반의 파형발생 및 신호처리를 혼합하여 최대탐지 가능 속도와 속도 보상에 대해 강점을 보유할 수 있도록 제작하였으며, 구현된 시스템은 실험실 내 시험과 실제 주행시험을 통하여 성능 및 상용화 가능성에 대한 분석을 진행하였다.