• Transactions of the Korean Society of Machine Tool Engineers
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• v.13 no.6
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• pp.1-9
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• 2004

For improvement of productivity and cutting tool lift, cutting force in end milling needs to be predicted accurately. In order to analyze cutting force, the cutting dynamics was modelled mathematically by using chip load, cutting geometry, and the relationship between cutting forces and the chip load. Specific cutting force coefficients of the cutting dynamics model were obtained by average cutting forces, tool diameter, cutting speed, fled, axial depth and radial depth of cut. The effects of the cutting conditions on the specific cutting force constants in milling were studied. The model is verified through comparisons of model predicted cutting forces with measured cutting forces obtained from machining experiments.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.1
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• pp.28-36
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• 2010

Hardware implementation methods for Artificial Neural Network (ANN) have been researched for a long time to achieve high performance. We have proposed a Network on Chip (NoC) for ANN, and this architecture can reduce communication load and increase performance when an implemented ANN is small. In this paper, a multiple NoC models are proposed for ANN, which can implement both a small size ANN and a large size one. The simulation result shows that the proposed multiple NoC models can reduce communication load, increase system performance of connection-per-second (CPS), and reduce system running time compared with the existing hardware ANN. Furthermore, this architecture is reconfigurable and reparable. It can be used to implement different applications of ANN.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.11a
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• pp.21-26
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• 2002

Solder flip chip bumping and subsequent coining processes on PCB were investigated to solve the warpage problem of organic substrates for high pin count flip chip assembly by providing good co-planarity. Coining of solder bumps on PCB has been successfully demonstrated using a modified tension/compression tester with height, coining rate and coining temperature variables. It was observed that applied loads as a function of coined height showed three stages as coining deformation : (1) elastic deformation at early stage, (2) linear increase of applied load, and (3) rapid increase of applied load. In order to reduce applied loads for coining solder bumps on PCB, effects of coining process parameters were investigated. Coining loads for solder bump deformation strongly depended on coining rates and coining temperatures. As coining rates decreased and process temperature increased, coining loads decreased. Among the effect of two factors on coining loads, it was found that process temperature had more significant effect to reduce applied coining loads during the coining process. Lower coining loads were needed to prevent substrate damages such as micro-via failure and build-up dielectric layer thickness change during applying loads. For flip chip assembly, 97Pb/Sn flip chip bumped devices were successfully assembled on organic substrates with 37Pb/Sn coined flip chip bumps.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1994.10a
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• pp.49-54
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• 1994

A dynamic model for the cutting process in the end milling process is developed. This model, which describes the dynamic response of the end mill, the chip load geometry including tool runout, the dependence of the cutting forces on the chip load, is used to predict the dynamic cutting force during the end milling process. In order to predict accurately cutting forces and tool vibration, the model, which uses instantaneous specific cutting force, includes both regenerative effect and penetration effect. The model is verified through comparisons of model predicted cutting force with measured cutting forces obtained from machining experiments.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.187-188
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• 2007

This paper describes a simple and high-performance LDO regulator designed using a $0.18{\mu}m$ CMOS process. It is designed to provide a regulated voltage for on-chip small loads instead of for off-chip heavy loads. Since the load capacitance is very small in this applications, the frequency compensation can be easily achieved without a buffer. The designed LDO drives a load current up to 15mA and dissipates only 12uA quiescent current. The line regulation is and the load regulation is for a 9mA load step. The PSRR at 10kHz is 54dB.

• Journal of Mechanical Science and Technology
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• v.14 no.6
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• pp.622-632
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• 2000

In a high precision vertical machining center, the estimation of cutting forces is important for many reasons such as prediction of chatter vibration, surface roughness and so on. The cutting forces are difficult to predict because they are very complex and time variant. In order to predict the cutting forces of end-milling processes for various cutting conditions, their mathematical model is important and the model is based on chip load, cutting geometry, and the relationship between cutting forces and chip loads. Specific cutting force coefficients of the model have been obtained as interpolation function types by averaging forces of cutting tests. In this paper the coefficients are obtained by neural network and the results of the conventional method and those of the proposed method are compared. The results show that the neural network method gives more correct values than the function type and that in the learning stage as the omitted number of experimental data increase the average errors increase as well.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.543-551
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• 2017

SOL (Short, Open and Load) calibration based on iterative error sensitivity is proposed in this paper. With advanced SOL calibration, unknown parasitic parameters at on-chip terminations are accurately estimated up to 20 GHz. Artificial terminations are designed on printed circuit board (PCB) to experiment the proposed method. On-chip SHORT, OPEN and LOAD fabricated inside silicon shows the accuracy of proposed calibration method through the comparison with known fixture S-parameter after de-embedding.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.8 no.3
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• pp.83-91
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• 1999

In this paper, we suggest a virtual machining system that can simulate cutting forces of ball end milling at the stage of part design. Cutting forces, here, are estimated from the machanistic model that uses the concept of specific cutting farce coefficient. To this end, we need undeformed chip thickness which is used for calculating chip load. It is derived from the Z-map data of a CAD model. That is, chip load is the height difference between the cutting tool and the workpiece at an arbitrary position. The tool contact point is referred from the cutter location data. On the other hand, the workpiece height is acquired from the Z-map model of a CAD data. From the experimental verification, we can simulate machining process effectively to the slot and the side cutting of ball end mill.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.04a
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• pp.942-946
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• 1997

In this research,we suggest a virtual machining system that can simulate sutting forces at the stage of design. Cutting forces,here, are modeled form the machanistic model of the ball end milling. To this end, we need undeformed chip thickness which is used for calculating chip load. It is derived form the z-map data of a CAD model. That is, chip load is the height difference between the cutting tool contact point and the workpiece at arbitrary position. The tool contact point is referred from the cutter location. Form the experimental verification, we can simulate machining process effectively to the slot and the side cutting of ball end mill.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.10
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• pp.881-886
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• 2003

This paper describes the design and implementation of a passive transponder chip for RFID applications. Passive transponders do not have their own power supply, and therefore all power required for the operation of a passive transponder must be drawn from the field of the reader. The designed transponder consists of a full wave rectifier to generate a dc supply voltage, a 128-bit mask ROM to store the information, and Manchester coding and load modulation circuits to be used for transmitting the information from the transponder to the reader. The transponder with a size 410 x 900 ${\mu}$m$^2$ has been fabricated using 0.65 ${\mu}$m 2-poly, 2-metal CMOS process. The measurement results show the data transmission rate of 3.9 kbps at RF frequency 125 kHz.