• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.38 no.6
• /
• pp.11-17
• /
• 2001

Design and implementation of the MAC protocol processor prototype for high speed wireless LAN, which has interface with 5GHz OFDM PHY layer, is presented. We analyze the IEEE 802.11 MAC protocol specification and then separate the MAC protocol functions to be implemented by hardware and firmware and define the interface in which frames can be exchanged. That is, it is considered that high speed queue processing and interfaces with RISC processor and OFDM PHY layer. Protocol control and transmission/reception functions of the MAC functions are implemented in hardware in order to guarantee high speed processing in MAC layer. The developed MAC hardware block operates at 10MHz main clock. Therefore, transmission rate in PHY layer is about 80Mbps because data transmission/reception between MAC layer and PHY layer is performed as unit of octet. The designed FPGA MAC function chip has been implemented in wireless LAN test board and it is verified that DCF function is operated correctly.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.38 no.5
• /
• pp.509-517
• /
• 2001

Full-search algorithm requires large amount of computation which causes time delay or very complex hardware architecture for real time implementation. In this paper, we propose a fast motion estimator based on bit-plane matching, which reduce the computational complexity and the hardware cost. In the proposed motion estimator, the conventional motion estimation algorithms are applied to the binary images directly extracted from the video sequence. Furthermore, in the proposed VLSI motion estimator, we employ a Pair of processing cores that calculate the motion vector continuously By controlling the data flow in a systolic fashion using the internal shift registers in the processing cores, we avoid using SRAM (local memory) so that we remove the time overhead for accessing the local memory and adopt lower-cost fabrication technology. We modeled and tested the proposed motion estimator in VHDL, and then synthesized the whole system which has been integrated in a 0.6-$\mu$m triple-metal CMOS chip of size 8.15 X 10.84$\textrm{mm}^2$.

• The Transactions of the Korea Information Processing Society
• /
• v.5 no.10
• /
• pp.2686-2703
• /
• 1998

The widening pClformnnce gap between processor and memory causes an emergence of the promising architecture, processor-memory (PM) integration In this paper, various design issues for P-M integration are studied, First, an analytical model of the DRAM access time is constructed considering both the bank conflict ratio and the DRAM page hit ratio. Then the points of both the performance improvement and the perfonnance bottle neck are found by the proposed model as designing on-chip DRAM architectures. This paper proposes the new architecture, called the delayed precharge bank architecture, to improve the perfonnance of memory system as increasing the DRAM page hit ratio. This paper also adapts an efficient bank interleaving mechanism to the proposed architecture. This architecture is verified !II he better than the hierarchical multi-bank architecture as well as the conventional bank architecture by executiun driven simulation. Eight SPEC95 benchmarks are used for simulation as changing parameters for the cache architecture, the number of DRAM banks, and the delayed time quantum.

• 제어로봇시스템학회:학술대회논문집
• /
• 2005.06a
• /
• pp.1439-1444
• /
• 2005

Induction motors are the most commonly used electrical drives because they are rugged, mechanically simple, adaptable to widely different operating conditions, and simple to control. The most common faults in squirrel-cage induction motors are bearing, stator and rotor faults. Surveys conducted by the IEEE and EPRI show that the most common fault in induction motor is bearing failure (${\sim}$40% of failure). Thence, this paper addresses experimental results for diagnosing faults with different rolling element bearing damage via motor current spectral analysis. Rolling element bearings generally consist of two rings, an inner and outer, between which a set of balls or rollers rotate in raceways. We set the experimental test bed to detect the rolling-element bearing misalignment of 3 type induction motors with normal condition bearing system, shaft deflection system by external force and a hole drilled through the outer race of the shaft end bearing of the four pole test motor. This paper takes the initial step of investigating the efficacy of current monitoring for bearing fault detection by incipient bearing failure. The failure modes are reviewed and the characteristics of bearing frequency associated with the physical construction of the bearings are defined. The effects on the stator current spectrum are described and related frequencies are also determined. This is an important result in the formulation of a fault detection scheme that monitors the stator currents. We utilized the FFT, Wavelet analysis and averaging signal pattern by inner product tool to analyze stator current components. The test results clearly illustrate that the stator signature can be used to identify the presence of a bearing fault.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.39 no.1
• /
• pp.7-15
• /
• 2002

This paper is concerned with remote environment monitoring & control for the breeding house as scattering far and wide. The environment data is detected in the breeding house that is collected to one processor. It's adapted to the PSTN(public switch tele-phone network) and multi-processing for exchange the environment data and the control data in between the manager and a breeding house by micro-processor. We have designed the algorithm of the communication sequence through the experimental research. This system is composed of sensor interface, FSK communications, LED display, data latch and MCS-51 single-chip. The S/W is composed with data acquisition by multi-processing, data communication and interrupt. And this paper is Proposed the DB structure algorithm concern to a mount scale using web design. The subject is a performance of effective management for the breeding house.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.10 s.352
• /
• pp.68-73
• /
• 2006

This, paper proposes a cosimulation methodology that results in an efficient SoC design as well as fast verification by integrating HDL, SystemC, and algorithm-level abstraction using the design tools Active-HDL and Matlab's Simulink. To demonstrate the proposed design methodology, we implemented the design technique on a serial connection multi-channel speaker system. We have demonstrated the proposed cosimulation method utilizing an ARM processor based SoC Master board with the AMBA bus interface and a Xilinx Vertex4 FPGA. The proposed method has the advantage of simultaneous simulation verification of both software and hardware parts in high levels of abstraction mixed with some performance critical parts in more concrete RTL codes. This allows relatively fast and easy design of a speaker connection system which typically requires significant amount of data processing for verification.

• The Transactions of the Korea Information Processing Society
• /
• v.3 no.5
• /
• pp.1346-1353
• /
• 1996

In this paper, we propose a modeling method for the flip-flops and test generation algorithms to detect the faults in the sequential circuits using VHDL in the high-level design environment. RS, JK, D and T flip-flops are modeled using data flow types. The sequence of micro-operation which is the basic structure of a chip-level leads to a control point where varnishing occurs to one of two micro- operation sequence. In order to model the fault of one micro-operation(FMOP) that perturb another micro-operation effectively, the concept of goal trees and some heuristic rules are used. Given a faulty FMOP or fault of control point (FCON), a test pattern is generated by fault sensitization, path sensitization and determination of the imput combinations that will justify the path sensitization. The fault models are restricted to the data flow model in the ARCHITECTURE statement of VHDL. The proposed algorithm is implemented in the C language and its efficiency is confirmed by some examples.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2006.08a
• /
• pp.647-650
• /
• 2006

Low temperature polycrystalline silicon (LTPS) technology using a high power laser have been widely applied to thin film transistors (TFTs) for liquid crystal, organic light emitting diode (OLED) display, driver circuit for system on glass (SOG) and static random access memory (SRAM). Recently, the semiconductor industry is continuing its quest to create even more powerful CPU and memory chips. This requires increasing of individual device speed through the continual reduction of the minimum size of device features and increasing of device density on the chip. Moreover, the flat panel display industry also need to be brighter, with richer more vivid color, wider viewing angle, have faster video capability and be more durable at lower cost. Kornic Systems Co., Ltd. developed the $KORONA^{TM}$ LTP/GLTP series - an innovative production tool for fabricating flat panel displays and semiconductor devices - to meet these growing market demands and advance the volume production capabilities of flat panel displays and semiconductor industry. The $KORONA^{TM}\;LTP/GLTP$ series using DPSS laser and XeCl excimer laser is designed for the new generation of the wafer & FPD glass annealing processing equipment combining advanced low temperature poly-silicon (LTPS) crystallization technology and object-oriented software architecture with a semistandard graphical user interface (GUI). These leading edge systems show the superior annealing ability to the conventional other method. The $KORONA^{TM}\;LTP/GLTP$ series provides technical and economical benefits of advanced annealing solution to semiconductor and FPD production performance with an exceptional level of productivity. High throughput, low cost of ownership and optimized system efficiency brings the highest yield and lowest cost per wafer/glass on the annealing market.

• Transactions of the Korean Society of Mechanical Engineers B
• /
• v.20 no.10
• /
• pp.3334-3343
• /
• 1996

A quantitative flow visualization technique was developed to measure velocity and temperature fields simultaneously in a two-dimensional cross section of thermo-fluid flows. Thermochromic liquid crystal(TLC) particles are used as temperature sensor and velocity tracers. Illuminating a thermo-fluid flow with a thin sheet of white light, the reflected colors from the TLC particles in the flow were captured simultaneously by two CCD cameras; a 3-chip CCD color camera for temperature field measurement and a black and white CCD camera for velocity field measurement. Variations of temperature field were measured by using a HSI true color image processing system and TLC solution. The relationship between the hue values of TLC color image and real temperature was obtained and this calibration curve was used to measure the true temperature under the same camera and illumination condition. The velocity field was obtained by using a 2-frame PTV technique using the concept of match-probability to track true velocity vectors from two consecutive image frames. These two techniques were applied at the same time to the unsteady thermal-fluid flow in a Hele-Shaw cell to measure the temperature and velocity field simultaneously and some results are discussed.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.4
• /
• pp.26-33
• /
• 2010

This paper presents a multi-channel capacitive touch sensing unit for SoC applications. This unit includes a simple common processing unit and switch array to detect the touch sensing input by capacitive-time(C-T) conversion method. This touch sensor ASIC is designed based on the Capacitive-Time(C-T) conversion method to have advantages of small current and chip area, and the minimum resolution of the unit is 41 fF per count with the built-in sensing oscillator, LDO regulator and $I^2C$ for no additional external components. This unit is implemented in 0.18 um CMOS process with dual supply voltage of 1.8 V and 3.3 V. The total power consumption of the unit is 60 uA and the area is 0.26 $mm^2$.