• 제목/요약/키워드: chip processing

검색결과 807건 처리시간 0.024초

FPGA를 이용한 심전도 전처리용 적응필터 설계 (Design of FPGA Adaptive Filter for ECG Signal Preprocessing)

  • 한상돈;전대근;이경중;윤형로
    • 대한의용생체공학회:의공학회지
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    • 제22권3호
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    • pp.285-291
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    • 2001
  • In this paper, we designed two preprocessing adaptive filter - high pass filter and notch filter - using FPGA. For minimizing the calculation load of multi-channel and high-resolution ECG system, we utilize FPGA rather than digital signal processing chip. To implement the designed filters in FPGA, we utilize FPGA design tool(Altera corporation, MAX-PLUS II) and CSE database as test data. In order to evaluate the performance in terms of processing time, we compared the designed filters with the digital filters implemented by ADSP21061(Analog Devices). As a result, the filters implemented by FPGA showed better performance than the filters based on ADSP21061. As a consequence of examination, we conclude that FPGA is a useful solution in multi-channel and high-resolution signal processing.

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가장자리 검출을 위한 상호연결을 가진 망막칩 (A novel reitna chip with simple wiring for edge extraction)

  • 심선일;김용태;박정호
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2000년도 추계종합학술대회 논문집(3)
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    • pp.153-156
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    • 2000
  • A novel silicon retina chip based on the information processing in the vertebrate retina was designed. The chip has a novel wiring structure in which all pixels are connected through the channel of MOS transistors, which simplifies a wiring structure compared with conventional resistive networks. The proposed structure minimizes the pixel area and certainly increases a fill factor since each pixel consists of only two photodiodes and three MOS transistors. It also enables the chip to operate over a wide range of light intensity by adjusting its conductance with the gate voltage. Simulation results with SPICE showed that the chip could extract the edge of input images successfully.

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플립칩 패키지에서 UBM 및 IMC 층의 형상 모델링 (Solid Modeling of UBM and IMC Layers in Flip Chip Packages)

  • 신기훈;김주한
    • 한국공작기계학회논문집
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    • 제16권6호
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    • pp.181-186
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    • 2007
  • UBM (Under Bump Metallurgy) of flip chip assemblies consists of several layers such as the solder wetting, the diffusion barrier, and the adhesion layers. In addition, IMC layers are formed between the solder wetting layers (e.g. Cu, Ni) and the solder. The primary failure mechanism of the solder joints in flip chips is widely known as the fatigue failure caused by thermal fatigues or electromigration damages. Sometimes, the premature brittle failure occurs in the IMC layers. However, these phenomena have thus far been viewed from only experimental investigations. In this sense, this paper presents a method for solid modeling of IMC layers in flip chip assemblies, thus providing a pre-processing tool for finite element analysis to simulate the IMC failure mechanism. The proposed modeling method is CSG-based and can also be applied to the modeling of UBM structure in flip chip assemblies. This is done by performing Boolean operations according to the actual sequences of fabrication processes

Micro EDM을 이용한 Lab-on-a-chip금형의 미세 패턴 제작에 관한 연구 (A Study on the Micro Pattern Fabrication of Lab-on-a-chip Mold Master using Micro EDM)

  • 신봉철;김규복;조명우;김보현;정우철;허영무
    • 소성∙가공
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    • 제20권1호
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    • pp.17-22
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    • 2011
  • Recently, analyzing system is studying for applying to biomedical engineering field, actively. Micro fluidics control system has been manufactured using LIGA (Lithographie Galvanoformung und Abformung), Etching, Lithography and Laser etc. However, it is difficult that above-mentioned methods are applied to fabrication of precision mold master efficiently because of long processing time and rising cost of equipments. Therefore, in this study, micro EDM and micro WEDG system were developed to analyze machining characteristics with tool wear, surface roughness and process time. Then, optimal machining conditions could be obtained from the results of analysis. As the results, mold master of staggered herringbone mixer which has a high mixing efficiency, one of passive mixer of Lab-on-a-chip, could be fabricated from micro pattern(< 50um) using micro EDM successfully.

초소형 RF-chip inductor의 외관 검사 알고리즘에 관한 연구 (A Study on the Vision Algorithm for the Inspection of very small RF-Chip Inductor)

  • 김기순;김기영;김준식
    • 융합신호처리학회논문지
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    • 제1권1호
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    • pp.89-96
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    • 2000
  • 본 논문에서는 이동 통신용 단말기에 주로 사용되는 RF-chip inductor의 자동 외관검사를 위한 시스템에 필요한 알고리즘을 제안하였다 제안한 방법은 취득한 영상에 국부적응 이진화 방법, 가산투영 기법을 적용하여 코일 부분과 코어 부분을 분리한다. 분리된 코일부분에 세선화(thinning) 방법, 체인코드(chain-code) 방법, 라벨링(labeling) 방법 등을 적용하여 코일성분을 추출하여 코일의 길이, 연결성, 코일의 turn수 그리고 피치간격에 의한 불균일 검사를 수행하여 소자의 불량 유무를 검사한다. 제안한 방법의 성능을 시험하기 위해 여러 가지 부품에 대한 모의실험을 통해 제안된 알고리즘의 성능을 검증하였다.

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On-Demand Remote Software Code Execution Unit Using On-Chip Flash Memory Cloudification for IoT Environment Acceleration

  • Lee, Dongkyu;Seok, Moon Gi;Park, Daejin
    • Journal of Information Processing Systems
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    • 제17권1호
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    • pp.191-202
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    • 2021
  • In an Internet of Things (IoT)-configured system, each device executes on-chip software. Recent IoT devices require fast execution time of complex services, such as analyzing a large amount of data, while maintaining low-power computation. As service complexity increases, the service requires high-performance computing and more space for embedded space. However, the low performance of IoT edge devices and their small memory size can hinder the complex and diverse operations of IoT services. In this paper, we propose a remote on-demand software code execution unit using the cloudification of on-chip code memory to accelerate the program execution of an IoT edge device with a low-performance processor. We propose a simulation approach to distribute remote code executed on the server side and on the edge side according to the program's computational and communicational needs. Our on-demand remote code execution unit simulation platform, which includes an instruction set simulator based on 16-bit ARM Thumb instruction set architecture, successfully emulates the architectural behavior of on-chip flash memory, enabling embedded devices to accelerate and execute software using remote execution code in the IoT environment.

다중 칩 수퍼스칼라 마이크로프로세서용 부동소수점 연산기의 설계 (Design of Floating-point Processing Unit for Multi-chip Superscalar Microprocessor)

  • 이영상;강준우
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1998년도 추계종합학술대회 논문집
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    • pp.1153-1156
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    • 1998
  • We describe a design of a simple but efficient floatingpoint processing architecture expoiting concurrent execution of scalar instructions for high performance in general-purpose microprocessors. This architecture employs 3 stage pipeline asyncronously working with integer processing unit to regulate instruction flows between two arithmetic units.

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CFRP Chip 표면처리에 따른 페놀복합재료의 강화, 내열성 및 난연성 향상 (Reinforcement, Thermal and Fire Retardant Improvement of Phenolic Composites by Surface Treatment of CFRP Chip)

  • 권동준;왕작가;구가영;박종만
    • 접착 및 계면
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    • 제13권2호
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    • pp.58-63
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    • 2012
  • 탄소섬유강화플라스틱(CFRP)의 홀 가공 시 chip이 발생된다. 이때 발생되는 chip은 단순 폐기용 차원이 아닌 미세탄소섬유와 에폭시의 조성으로 이루어져 있다. Chip을 강화재로 활용하기 위해서는 탄소섬유만의 조성을 이루어야 고분자 기지와 계면접착력이 증가될 수 있다. Chip 내 탄소섬유의 길이를 일정하게 하기 위해 막자 사발을 이용한 절단 과정 후 $H_2O_2$를 이용한 표면처리를 하여 탄소섬유에 붙어있는 에폭시를 제거하였다. Chip을 이용하여 페놀수지를 기지로 한 페놀복합재료를 제조하였으며, 내열성 및 난연성 재료로 활용 가능성을 평가하였다. 기존의 페놀보다 표면처리를 한 chip복합재료가 기계적, 열적 물성이 향상됨을 확인하였으며, 젖음성 평가를 이용하여 표면물성에 따른 재료의 물성을 평가하였다. 불균질한 표면 조성에 의해 표면 거칠기가 달라지기 때문에 페놀복합재료의 접촉각이 증가되었다. 난연성 평가는 ASTM D635-06 방법으로 수행하였다. 평가결과, chip의 첨가 및 표면처리의 영향에 의해 난연성이 향상되었다.

A Study on the Cutting Characteristics of the Glass Fiber Reinforced Plastics by Drill Tools

  • Park, Jong-Nam;Cho, Gyu-Jae
    • International Journal of Precision Engineering and Manufacturing
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    • 제8권1호
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    • pp.11-15
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    • 2007
  • Composite materials are widely used to make all kinds of machine parts, internal and structural materials of cars, aerospace components, building structures, ship materials, sporting goods and others, It is worth while to use composite space substitute material in various applications when compared with others. But the use of composite material is limited in the field of the mechanical processing because of the difficulties in processing. Thus, it is proved that the surface is rough at the in and out sections of the hole processing when the GFRP is machined with HSS drill in the vertical machining center. And it is observed that the more it is processed, the more the fluid type long chip is changed into the powdered chip.

Optimization of the Processing Parameters for Green Banana Chips and Packaging within Polyethylene Bags

  • Mitra, Pranabendu;Kim, Eun-Mi;Chang, Kyu-Seob
    • Food Science and Biotechnology
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    • 제16권6호
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    • pp.889-893
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    • 2007
  • The demand of quality green banana chips is increasing in the world snacks market, therefore, the preparation of quality chips and their subsequent shelf life in packaging were evaluated in this study. Banana slices were fried in hot oil to the desired moisture content (2-3%) and oil content (40%) in chips at 3 different temperatures, and the impact of different pretreatments were compared by sensory assessment. A linear relationship between time and temperature was used to achieve the optimal processing conditions. Banana slices fried at the lower temperature of $145^{\circ}C$ took longer to reach the desired chip qualities, but gave the best results in terms of color and texture. Blanching was the most effective pre-treatment for retaining the light yellow color in finished chips. For extending the shelf life of chips, moisture proof packaging in double layer high density polyethylene was more effective than single layer low density polyethylene.