• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.309-312
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• 2001

A primitive gas classification system which can classify limited species of gas was designed and simulated. The 'electronic nose' consists of an array of 4 metal oxide gas sensors with different selectivity patterns, signal collecting unit and a signal pattern recognition and decision Part in PLD(programmable logic device) chip. Sensor array consists of four commercial, tin oxide based, semiconductor type gas sensors. BP(back propagation) neutral networks with MLP(Multilayer Perceptron) structure was designed and implemented on CPLD of fifty thousand gate level chip by VHDL language for processing the input signals from 4 gas sensors and qualification of gases in air. The network contained four input units, one hidden layer with 4 neurons and output with 4 regular neurons. The 'electronic nose' system was successfully classified 4 kinds of industrial gases in computer simulation.

• Journal of the Korean Society for Precision Engineering
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• v.6 no.4
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• pp.61-70
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• 1989

A new analytical method is proposed to monitor the chip form of cutting forces applying the techinque of signal process. Cutting experiments are carried out under various cutting conditons and cutting forces are measured in-processing through Tool Dynamometer. In this report, auto-correlation functions, frequency characteristics of dynamic force, high frequency distribution and Peak/RMS values are calculated from the measured cutting forces, and the concept of method is also discussed. The experimental results show that six types of the form of chips are possible to classify from the signal of cutting forces not related to cutting conditions.

• Journal of the Korean Society for Precision Engineering
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• v.17 no.7
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• pp.217-225
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• 2000

Scanning Acoustic Microscope (SAM) is used as an important nondestructive test tool in semiconductor reliability evaluation and failure analysis. However, inspections of chip attach adhesive interface fer thin chip has proven difficulty as the reflected signals from the chip top and bottom are superimposed. In this paper, in order to overcome this difficulty, a new signal processing method based on the deconvolution technique combined with the wavelet transform is proposed. The wavelet transform complements a disability of deconvolution technique of which performance largely decreases when the waveform of target signal is not identical to that of reference signal. Performances of the proposed method are demonstrated by through computer simulations using model signal and experiments for the fabricated semiconductor samples, and satisfactory results are obtained.

• Journal of Electrical Engineering and information Science
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• v.2 no.3
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• pp.1-6
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• 1997

This paper describes the design of a network interface controller (NIC) chip which is to be used to support a novel adaptive virtual cut-through routing method for parallel compute systems with direct (i.e., point-to-point) interconnection networks. The NIC chip is designed to provide the interface between a processing node constructed from commercially available microprocessors and another custom-designed router chip, which in turn performs the actual routing of packets to their respective destinations. The NIC, designed using a semi-full-custom VLSi design technique outperform traditional wormhole routing with a minimal amount of hardware overhead. The NIC design has been fully simulated and laid out using a 0.8$\mu\textrm{m}$ CMOS process.

• Proceedings of the KIEE Conference
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• 1998.07e
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• pp.1696-1698
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• 1998

Pulsed Nd:YAG laser using Nd:YAG crystal operates stably in the thermal conductivity, mechanical, optical condition. That is used broadly in material processings because of easy reaction to the materials, and the maintenance is very easy because of lamp excitation. In these material processings, power dinsity control is very important to improve processing technology. Power density is controled by inductance and capacitance or repetition rate. Therefore we are going to control laser power density as One-Chip Microprocessor(PIC16C55) and 8051. We have been experimented at the pulse repetition rate range of 10pps to 60pps(pulse per second).

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1428-1431
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• 2002

It is general opinion that the future mobile multimedia networks will use different standards and a prospective solution to this problem will be software defined radio (SDR) techniques. SDR provides the flexibility to support multiple air interfaces and signal processing functions at the same time. Especially, digital signal processors and FPGAs are widely used for implementation of these adaptive and flexible functions of a baseband modem for SDR applications. Also, it is known that the modulation schemes of OCQPSK (Orthogonal Complex QPSK) and HPSK (Hybrid PSK) are used for IMT-2000 services of cdma2000 and WCDMA, respectively. Thus, in this paper, we design and implement an OCQPSK / HPSK modem using a DSP chip of Texas Instrument's TMS320C6701. One modulation scheme is operated by adaptive selection between the two schemes and 5 physical traffic channels differentiated by orthogonal codes are implemented in one DSP chip and each channel has 1Mbps data rates and 8Mcps chip rates.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.52 no.4
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• pp.148-153
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• 2003

In this paper, the low voltage 3V Sigma-Delta Digital Analog Converter(DAC) is designed for using in the transmitter of ADSL analog front-end. We have developed the CMOS DAC according to ANSI T1.413-2(DMT) standard specifications of the chip. The designed 4th-order DAC is composed of three block which are 1-bit DAC, 1st-order Switched-Capacitor filter and analog active 2nd-order Resistor-Capacitor(RC) filter. The HSPICE simulation of the designed DAC showing 65db SNR, is connected with 1.1MHz continuous lowpass filter. And also, we have performed the circuits verification and layout verification(ERC, DRC, LVS) followed by fabrication using TSMC 2-poly 5-metal p-substrate CMOS $0.35{\mu}m$ processing parameter. Finally, the chip testing has been performed and presented in the results.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.12
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• pp.9-19
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• 1997

This paper describes the design and FPGA implementation of a system control unit within a multiprocessor chip which can be used as a node processor ina massively parallel processing (MPP) caches, memory management units, a bus unit and a system control unit. Major functions of the system control unit are locking/unlocking of the shared variables of protected access, synchronization of instruction execution among four integer untis, control of interrupts, generation control of processor's status, etc. The system control unit was modeled in very high level using verilog HDL. Then, it was simulated and verified in an environment where trap handler and external interrupt controller were added. Functional blocks of the system control unit were changed into RTL(register transfer level) model and synthesized using xilinx FPGA cell library in synopsys tool. The synthesized system control unit was implemented by Xilinx FPGA chip (XC4025EPG299) after timing verification.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.93-100
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• 2003

The continuing scaling trend in microelectronic circuit technology has a significant impact on the different IC interconnection and packaging technologies. These latter technologies have not kept pace with the IC scaling trends, resulting in a so-called“interconnect technology gap”. Multilayer thin film technology is proposed as a“bridge”- technology between the very high density IC technology and the coarse standard PCB technology. It is also a key enabling technology for the realisation of true“System-in-a-Package”(SIP) solutions, combining multiple“System-on-a-Chip”(SOC) IC's with other components and also integrating passive components in its layers. A further step is to use this technology to realise new functionalities on top of active wafers. These additional“above-IC”processed layers may e.g. be used for low loss, high speed on chip interconnects, clock distribution circuits, efficient power/ground distribution and to realize high Q inductors on chip.

• Journal of the Korean Society for Precision Engineering
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• v.7 no.2
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• pp.47-57
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• 1990

In-process recognition of the cutting states is one of the very important technologies to increase the reliability of mordern machining process. In this study, practical methods which use the dynamic component of the cutting force are proposed to recognize cutting states (i.e. chip formation, tool wear, surface roughness) in turning process. The signal processing method developed in this study is efficient to measure the maximum amplitude of the dynamic component of cutting force which is closely related to the chip breaking (cut-off frequency : 80-500 Hz) and the approximately natural frequency of cutting tool (5, 000-8, 000 Hz). It can be clarified that the monitoring of the maximum apmlitude in the dynamic component of the cutting force enables the state of chip formation which chips can be easily hancled and the inferiority state of the machined surface to be recognized. The microcomputer in-process tool wear monitor- ing system introduced in this paper can detect the determination of the time to change cutting tool.